Comparator, circuit device, physical quantity sensor, electronic device, and vehicle

Patent metadata

Field	Value
Publication number	US-10122377-B2
Application number	US-201715848269-A
Country	US
Kind code	B2
Filing date	Dec 20, 2017
Priority date	Jul 25, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A comparator includes a first voltage-time conversion circuit, a second voltage-time conversion circuit, and a determination circuit. A first delay unit includes a first primary conductivity type transistor of which current is controlled based on a first input signal, a first secondary conductivity type transistor of which current is controlled based on a second input signal, and a first delay buffer provided between the transistors. A second delay unit includes a second primary conductivity type transistor of which current is controlled based on a second input signal, a second secondary conductivity type transistor of which current is controlled based on a first input signal, and a second delay buffer provided between the transistors.

First claim

What is claimed is:

1. A comparator comprising:
a first voltage-time conversion circuit which includes a first delay circuit, the first delay circuit being configured to receive a first input signal and a second input signal;
a second voltage-time conversion circuit which includes a second delay circuit, the second delay circuit being configured to receive the first input signal and the second input signal; and
a determination circuit communicating with the first and second voltage-time conversion circuits, the determination circuit being configured to determine a magnitude relation of the first input signal and the second input signal, based on an output signal of the first voltage-time conversion circuit and an output signal of the second voltage-time conversion circuit,
wherein the first delay circuit includes a first delay unit, the first delay unit including:
a first primary conductivity type transistor, a current of the first primary conductivity type transistor being controlled based on the first input signal,
a first secondary conductivity type transistor, a current of the first secondary conductivity type transistor being controlled based on the second input signal, and
a first delay buffer circuit connected to the first primary conductivity type transistor and the first secondary conductivity type transistor, the first delay buffer circuit being configured to delay an input signal received by the first delay unit and generate a first delayed output signal based on the first input signal and the second input signal, and

wherein the second delay circuit includes a second delay unit, the second delay unit including:
a second primary conductivity type transistor, a current of the second primary conductivity type transistor being controlled based on the second input signal,
a second secondary conductivity type transistor, a current of the second secondary conductivity type transistor being controlled based on the first input signal, and
a second delay buffer circuit connected to the second primary conductivity type transistor and the second secondary conductivity type transistor, the second delay buffer circuit being configured to delay an input signal received by the second delay unit and generate a second delayed output signal based on the first input signal and the second input signal.

2. The comparator according to claim 1 ,
wherein the first delay circuit includes a plurality of the first delay units connected in series; and
the second delay circuit includes a plurality of the second delay units connected in series.

3. The comparator according to claim 2 ,
wherein in the first delay circuit, the first primary conductivity type transistor and the first secondary conductivity type transistor are shared between at least two delay units of the plurality of delay units, and
wherein in the second delay circuit, the second primary conductivity type transistor and the second secondary conductivity type transistor are shared between at least two delay units of the plurality of delay units.

4. The comparator according to claim 1 ,
wherein in a case where a determination result of the determination circuit is confirmed, power supply voltages to be supplied to the first delay buffer circuit and the second delay buffer circuit are set to a predetermined voltage.

5. The comparator according to claim 1 ,
wherein a delay time of the first delay buffer circuit is controlled based on a current flowing through any one of the first primary conductivity type transistor and the first secondary conductivity type transistor, and
wherein a delay time of the second delay buffer circuit is controlled based on a current flowing through any one of the second primary conductivity type transistor and the second secondary conductivity type transistor.

6. The comparator according to claim 1 ,
wherein the first voltage-time conversion circuit further includes
a first input signal generation circuit that generates the input signal received by the first delay circuit, and
a first latch circuit configured to operate based on an output signal of the first delay circuit, and

wherein the second voltage-time conversion circuit further includes
a second input signal generation circuit that generates the input signal received by the second delay circuit, and
a second latch circuit configured to operate based on an output signal of the second delay circuit.

7. The comparator according to claim 6 ,
wherein the first input signal generation circuit is configured to change the input signal input to the first delay unit from a first logic level to a second logic level, and to change the input signal input to the first delay unit from the second logic level to the first logic level, in a case where the output signal of the first delay circuit changes from the first logic level to the second logic level,
wherein the first latch circuit is configured to change the output signal of the first voltage-time conversion circuit from the second logic level to the first logic level, in a case where the output signal of the first delay circuit changes from the second logic level to the first logic level,
wherein the second input signal generation circuit is configured to change the input signal input to the second delay unit from the first logic level to the second logic level, and to change the input signal input to the second delay unit from the second logic level to the first logic level, in a case where the output signal of the second delay circuit changes from the first logic level to the second logic level, and
wherein the second latch circuit is configured to change the output signal of the second voltage-time conversion circuit from the second logic level to the first logic level, in a case where the output signal of the second delay circuit changes from the second logic level to the first logic level.

8. The comparator according to claim 1 ,
wherein the first voltage-time conversion circuit further includes a first measurement circuit that measures a number of pulses of an output signal from the first delay circuit,
wherein the output signal of the first voltage-time conversion circuit is generated based on a measurement result of the first measurement circuit,
wherein the second voltage-time conversion circuit further includes a second measurement circuit that measures a number of pulses of an output signal from the second delay circuit, and
wherein the output signal of the second voltage-time conversion circuit is generated based on a measurement result of the second measurement circuit.

9. The comparator according to claim 8 ,
wherein the first voltage-time conversion circuit further includes a first ring oscillator which includes the first delay circuit, and in which the output signal from the first delay circuit is fed back to the input signal received by the first delay unit, and
wherein the second voltage-time conversion circuit further includes a second ring oscillator which includes the second delay circuit, and in which the output signal from the second delay circuit is fed back to the input signal received by the second delay unit.

10. The comparator according to claim 9 ,
wherein the first voltage-time conversion circuit further includes a third input signal generation circuit that receives an enable signal and a signal based on the output signal from the first delay circuit, and generates the input signal received by the first delay unit, and
wherein the second voltage-time conversion circuit further includes a fourth input signal generation circuit that receives the enable signal and a signal based on the output signal of the second delay circuit, and generates the input signal received by the

Assignees

• Seiko Epson Corp

Inventors

• Haneda Hideo

Classifications

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/46

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03K5/249

  using clock signals · CPC title

• H03K9/08

  of duration- or width-mudulated pulses {or of duty-cycle modulated pulses} · CPC title