Dynamic biasing circuitry for level-shifter circuitry

US10122362B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10122362-B2
Application numberUS-201715485044-A
CountryUS
Kind codeB2
Filing dateApr 11, 2017
Priority dateApr 11, 2017
Publication dateNov 6, 2018
Grant dateNov 6, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In some examples, a device includes level-shifter circuitry and biasing circuitry including at least four diodes, wherein each diode of the at least four diodes is electrically connected in series. The biasing circuitry further includes push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to generate an intermediate voltage signal. The biasing circuitry is configured to deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a high-side voltage signal from the at least four diodes. The biasing circuitry is further configured to deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a low-side voltage signal from the at least four diodes.

First claim

Opening claim text (preview).

What is claimed is: 1. A device comprising: level-shifter circuitry; and biasing circuitry comprising: at least four diodes, wherein each diode of the at least four diodes is electrically connected in series; and push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to generate an intermediate voltage signal, wherein the biasing circuitry is configured to: deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a high-side voltage signal from the at least four diodes, and deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a low-side voltage signal from the at least four diodes. 2. The device of claim 1 , wherein the biasing circuitry further comprises: a high-side capacitor; and a low-side capacitor, wherein the push-pull circuitry is further configured to deliver the intermediate voltage signal to the high-side capacitor and the low-side capacitor, wherein the biasing circuitry is configured to deliver the high-side biasing signal based on the intermediate voltage signal delivered to the high-side capacitor, and wherein the biasing circuitry is configured to deliver the low-side biasing signal based on the intermediate voltage signal delivered to the low-side capacitor. 3. The device of claim 2 , wherein the biasing circuitry further comprises: a high-side filter resistor electrically connected to the at least four diodes and the high-side capacitor; and a low-side filter resistor electrically connected to the at least four diodes and the low-side capacitor, wherein the biasing circuitry is configured to deliver the high-side biasing signal to the level-shifter circuitry based on the high-side voltage signal received from the high-side filter resistor, and wherein the biasing circuitry is configured to deliver the low-side biasing signal to the level-shifter circuitry based on the low-side voltage signal received from the low-side filter resistor. 4. The device of claim 1 , wherein the level-shifter circuitry is first level-shifter circuitry, wherein the push-pull circuitry is first push-pull circuitry, wherein the intermediate voltage signal is a first intermediate voltage signal, wherein the high-side biasing signal is a first high-side biasing signal, wherein the low-side biasing signal is a first low-side biasing signal, wherein the high-side voltage signal is a first high-side voltage signal, and wherein the low-side voltage signal is a first low-side voltage signal, the device further comprising second level-shifter circuitry, wherein the biasing circuitry further comprises second push-pull circuitry electrically connected to the at least two diodes of the at least four diodes and configured to generate a second intermediate voltage signal, wherein the biasing circuitry is further configured to: deliver a second high-side biasing signal to the second level-shifter circuitry based on the second intermediate voltage signal and a second high-side voltage signal from the at least four diodes, and deliver a second low-side biasing signal to the second level-shifter circuitry based on the second intermediate voltage signal and a second low-side voltage signal from the at least four diodes. 5. The device of claim 4 , further comprising a first high-side capacitor, a first low-side capacitor, a second high-side capacitor, and a second low-side capacitor, wherein the first push-pull circuitry is further configured to deliver the first intermediate voltage signal to the first high-side capacitor and the first low-side capacitor, wherein the biasing circuitry is configured to deliver the first high-side biasing signal based on the first intermediate voltage signal delivered to the first high-side capacitor, wherein the biasing circuitry is configured to deliver the first low-side biasing signal based on the first intermediate voltage signal delivered to the first low-side capacitor, wherein the second push-pull circuitry is further configured to deliver the second intermediate voltage signal to the second high-side capacitor and the second low-side capacitor, wherein the biasing circuitry is configured to deliver the second high-side biasing signal based on the second intermediate voltage signal delivered to the second high-side capacitor, and wherein the biasing circuitry is configured to deliver the second low-side biasing signal based on the second intermediate voltage signal delivered to the second low-side capacitor. 6. The device of claim 1 , further comprising floating voltage supply circuitry and low-side voltage supply circuitry, wherein the biasing circuitry further comprises: at least one high-side biasing resistor electrically connected in series between the floating voltage supply circuitry and the at least four diodes; and at least one low-side biasing resistor electrically connected in series between the at least four diodes and the low-side voltage supply circuitry. 7. The device of claim 6 , further comprising: auxiliary voltage supply circuitry; a clamping diode; and at least two blocking diodes electrically connected in series between the auxiliary voltage supply circuitry and the floating voltage supply circuitry, wherein the at least two blocking diodes are configured to deliver a voltage signal from the auxiliary voltage supply circuitry to the floating voltage supply circuitry, wherein the push-pull circuitry is further configured to deliver the intermediate voltage signal through the clamping diode to an intermediate node of the at least two blocking diodes. 8. The device of claim 6 , wherein the level-shifter circuitry comprises: a first set of switches electrically connected in series between the floating voltage supply circuitry and the low-side voltage supply circuitry, wherein the first set of switches includes first cascode circuitry configured to receive the high-side biasing signal and the low-side biasing signal; and a second set of switches electrically connected in series between the floating voltage supply circuitry and the low-side voltage supply circuitry, wherein the second set of switches includes second cascode circuitry configured to receive the high-side biasing signal and the low-side biasing signal. 9. The device of claim 8 , wherein the first cascode circuitry comprises a first high-side switch and a first low-side switch, wherein the second cascode circuitry comprises a second high-side switch and a second low-side switch, wherein a control terminal of the first high-side switch and a control terminal of the second high-side switch are configured to receive the high-side biasing signal, and wherein a control terminal of the first low-side switch and a control terminal of the second low-side switch are configured to receive the low-side biasing signal. 10. The device of claim 6 , wherein a voltage difference between the intermediate voltage signal and the low-side voltage supply circuitry is approximately one-half of a voltage difference between the floating voltage supply circuitry and the low-side voltage supply circuitry. 11. The device of claim 6 , wherein the biasing circuitry further comprises a bootstrap capacitor electrically connected in parallel with the at least one high-side biasing resistor. 12. The device of claim 1 , wherein each diode of the at least four diodes is a diode-connected metal-oxide-semiconductor transistor. 13. The device of claim 1 , further comprising: half-bridge circuitry comprising a high-side power switch and a low-side power switch, wherein a switch node is electrical

Assignees

Inventors

Classifications

  • Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

  • of complementary type, e.g. CMOS · CPC title

  • for the simultaneous control of series or parallel connected semiconductor devices · CPC title

  • H02M1/08Primary

    Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

  • Circuits specially adapted for rendering non-conductive gas discharge tubes or equivalent semiconductor devices, e.g. thyratrons, thyristors · CPC title

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What does patent US10122362B2 cover?
In some examples, a device includes level-shifter circuitry and biasing circuitry including at least four diodes, wherein each diode of the at least four diodes is electrically connected in series. The biasing circuitry further includes push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to generate an intermediate voltage signal. The bia…
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H03K19/018521. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).