Electrostatic discharge protection for level-shifter circuit

Patent metadata

Field	Value
Publication number	US-9466978-B2
Application number	US-201314031826-A
Country	US
Kind code	B2
Filing date	Sep 19, 2013
Priority date	Aug 30, 2013
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A circuit, a multiple power domain circuit, and a method are disclosed. An embodiment is a circuit including an input circuit having a first output and a second output, the input circuit being coupled to a first power supply voltage, and a level-shifting circuit having a first input coupled to the first output of the input circuit and a second input coupled to the second output of the input circuit, the level-shifting circuit being coupled to a second power supply voltage. The circuit further includes a first transistor coupled between a first node of the level-shifting circuit and the second power supply voltage, and a control circuit having an output coupled to a gate of the first transistor, the control circuit being coupled to the second power supply voltage.

First claim

What is claimed is:

1. A circuit comprising:
an input circuit having a first output and a second output, the input circuit being coupled to a first power supply voltage;
a level-shifting circuit having a first input coupled to the first output of the input circuit and a second input coupled to the second output of the input circuit, the level-shifting circuit being coupled to a second power supply voltage;
a first transistor coupled between a first node of the level-shifting circuit and the second power supply voltage; and
a control circuit having an output coupled to a gate of the first transistor, the control circuit being coupled to the second power supply voltage, the control circuit being configured to turn off the first transistor in response to an electrostatic discharge (ESD) event.

2. The circuit of claim 1 , wherein the second power supply voltage comprises a second upper supply voltage and a second lower supply voltage, the first transistor being coupled between the first node of the level-shifting circuit and the second lower supply voltage.

3. The circuit of claim 2 , wherein the control circuit further comprises:
an inverter; and
a resistor having a first terminal directly connected to an input terminal of the inverter and a second terminal directly connected to the second lower supply voltage.

4. The circuit of claim 2 , wherein the control circuit further comprises:
a resistor directly connected between the second upper supply voltage and the gate of the first transistor; and
a capacitor directly connected between the second lower supply voltage and the gate of the first transistor.

5. The circuit of claim 2 further comprising a non-parasitic capacitor coupled between the output of the control circuit and the second lower supply voltage.

6. The circuit of claim 1 , wherein the level-shifting circuit further comprises:
a second transistor having:
a gate coupled to the first input of the level-shifting circuit;
a source coupled to the first node of the level-shifting circuit; and
a drain coupled to a second node of the level-shifting circuit;

a third transistor having:
a gate coupled to the second input of the level-shifting circuit;
a source coupled to the first node of the level-shifting circuit; and
a drain coupled to a third node of the level-shifting circuit;

a fourth transistor having:
a gate coupled to the third node of the level-shifting circuit;
a drain coupled to the second node of the level-shifting circuit; and
a source coupled to the second power supply voltage; and

a fifth transistor having:
a gate coupled to the second node of the level-shifting circuit;
a drain coupled to the third node of the level-shifting circuit; and
a source coupled to the second power supply voltage.

7. The circuit of claim 6 , wherein the level-shifting circuit further comprises:
a sixth transistor coupled between the second node of the level-shifting circuit and the drain of the fourth transistor; and
a seventh transistor coupled between the third node of the level-shifting circuit and the drain of the fifth transistor.

8. The circuit of claim 7 , wherein the sixth and seventh transistors are P-type transistors.

9. The circuit of claim 6 , wherein the first, second, and third transistors are N-type transistors, and wherein the fourth and fifth transistors are P-type transistors.

10. The circuit of claim 1 further comprising an inverter coupled between the first input and the second input of the level-shifting circuit.

11. The circuit of claim 1 , wherein the second power supply voltage is greater than the first power supply voltage.

12. A multiple power domain circuit comprising:
an input circuit in a first power domain;
a level-shifting unit coupled to an output terminal of the input circuit, the level-shifting unit being in a second power domain, the second power domain being different than the first power domain;
a first transistor coupled between a first node of the level-shifting unit and a ground node of the second power domain; and
a control unit configured to generate a control signal to a gate of the first transistor, the control unit being in the second power domain, the control unit being configured to present high impedance to the first node of the level-shifting unit in response to an electrostatic discharge (ESD) event.

13. The circuit of claim 12 , wherein the control unit further comprises a capacitor coupled between the gate of the first transistor and the ground node of the second power domain, wherein the capacitor is separate from the first transistor.

14. The circuit of claim 12 , wherein the level-shifting unit further comprises:
a pair of N-type transistors each having a gate coupled to the output terminal of the input circuit, the pair of N-type transistors each having a source coupled to the first node of the level-shifting unit; and
a pair of cross-coupled P-type transistors each having a source coupled to a power node of the second power domain, the pair of cross-coupled P-type transistors each having a drain coupled to the drain of one of the pair of N-type transistors.

15. The circuit of claim 12 further comprising a second transistor coupled between the first node of the level-shifting unit and a drain of the first transistor.

16. The circuit of claim 15 , wherein the first and second transistor are both N-type transistors.

17. A circuit comprising:
an input circuit in a first power domain;
a level-shifting circuit coupled to an output terminal of the input circuit, the level-shifting circuit being in a second power domain, the second power domain being different than the first power domain, the level-shifting circuit comprising:
a pair of N-type transistors each having a gate coupled to the output terminal of the input circuit, the pair of N-type transistors each having a source coupled to a first node of the level-shifting circuit, and
a pair of cross-coupled P-type transistors each having a source coupled to a power node of the second power domain, the pair of cross-coupled P-type transistors each having a drain coupled to the drain of one of the pair of N-type transistors,

a first transistor coupled between the first node of the level-shifting circuit and a ground node of the second power domain; and
a control circuit having an output coupled to a gate of the first transistor, the control circuit being in the second power domain, the control circuit being configured to turn off the first transistor and leave the sources of the pair of N-type transistors floating in response to an electrostatic discharge (ESD) event.

18. The circuit of claim 17 , wherein the control circuit further comprises a non-parasitic capacitor coupled between the gate of the first transistor and the ground node of the second power domain.

19. The circuit of claim 17 further comprising a second transistor coupled between the first node of the level-shifting circuit and a drain of the first transistor.

20. The circuit of claim 19 , wherein the first and second transistor are both N-type transistors.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chia-Hui
• Chu Chia-Hung
• Chen Kuo-Ji
• Song Ming-Hsiang
• Lu Lee-Chung

Classifications

• H03K19/017509

  Interface arrangements · CPC title

• H03K19/003

  Modifications for increasing the reliability {for protection} · CPC title

• H10D89/819

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/811

  using FETs as protective elements · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title