Semiconductor switch

Patent metadata

Field	Value
Publication number	US-10122356-B2
Application number	US-201715450985-A
Country	US
Kind code	B2
Filing date	Mar 6, 2017
Priority date	Sep 20, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A semiconductor switch includes a plurality of first terminals, a second terminal commonly provided for the plurality of first terminals, a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.

First claim

The invention claimed is:

1. A semiconductor switch comprising:
a plurality of first terminals;
a second terminal commonly provided for the plurality of first terminals;
a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and including MIS switches directly connected to the plurality of first terminals and ground; and
a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.

2. The semiconductor switch according to claim 1 , further comprising:
a plurality of second MIS switches formed on the SOI substrate, and connected between the plurality of first terminals and a reference voltage source, respectively.

3. The semiconductor switch according to claim 2 , further comprising:
a diode connected in parallel to the capacitor, and formed on the SOI substrate.

4. The semiconductor switch according to claim 3 ,
wherein an anode of the diode is connected to a node between the capacitor and the plurality of first MIS switches,
wherein a cathode of the diode is connected to a node between the capacitor and the second terminal.

5. The semiconductor switch according to claim 4 , further comprising:
an amplifier connected to the second terminal;
wherein a withstand voltage between the cathode and the anode is higher than an output voltage of the amplifier connected to the second terminal.

6. The semiconductor switch according to claim 5 ,
wherein the plurality of the first switches, the capacitor, and the diode are formed on the SOI substrate.

7. The semiconductor switch according to claim 4 , further comprising:
an amplifier connected to the second terminal;
wherein a withstand voltage between the cathode and the anode is higher than an output voltage of the amplifier connected to the second terminal.

8. The semiconductor switch according to claim 3 ,
wherein the diode is a MISFET (Metal Isolation Semiconductor Field Effect Transistor) including a gate, a source, and a drain, the gate is connected to the source, the source is connected to a node between the capacitor and the plurality of the first switches, and the drain is connected to a node between the capacitor and the second terminal.

9. The semiconductor switch according to claim 3 ,
wherein the plurality of the first switches, the capacitor, and the diode are formed on the SOI substrate.

10. The semiconductor switch according to claim 1 , further comprising:
a diode connected in parallel to the capacitor, and formed on the SOI substrate.

11. The semiconductor switch according to claim 10 ,
wherein an anode of the diode is connected to a node between the capacitor and the plurality of first MIS switches,
wherein a cathode of the diode is connected to a node between the capacitor and the second terminal.

12. The semiconductor switch according to claim 11 , further comprising:
an amplifier connected to the second terminal;
wherein a withstand voltage between the cathode and the anode is higher than an output voltage of the amplifier connected to the second terminal.

13. The semiconductor switch according to claim 12 ,
wherein the diode is a MISFET (Metal Isolation Semiconductor Field Effect Transistor) including a gate, a source, and a drain, the gate is connected to the source, the source is connected to a node between the capacitor and the plurality of the first switches, and the drain is connected to a node between the capacitor and the second terminal.

14. The semiconductor switch according to claim 12 ,
wherein the plurality of the first switches, the capacitor, and the diode are formed on the SOI substrate.

15. The semiconductor switch according to claim 10 , further comprising:
an amplifier connected to the second terminal;
wherein a withstand voltage between the cathode and the anode is higher than an output voltage of the amplifier connected to the second terminal.

16. The semiconductor switch according to claim 10 ,
wherein the diode is a MISFET (Metal Isolation Semiconductor Field Effect Transistor) including a gate, a source, and a drain, the gate is connected to the source, the source is connected to a node between the capacitor and the plurality of the first switches, and the drain is connected to a node between the capacitor and the second terminal.

17. The semiconductor switch according to claim 10 ,
wherein the plurality of the first switches, the capacitor, and the diode are formed on the SOI substrate.

18. The semiconductor switch according to claim 1 ,
wherein the capacitor is a MIS capacitor.

19. The semiconductor switch according to claim 1 ,
wherein the capacitor is a transistor formed on the SOI substrate,
wherein the transistor includes a gate insulating film, a gate electrode, and an impurity region formed under the gate insulating film and in the SOI substrate.

20. The semiconductor switch according to claim 1 ,
wherein the capacitor includes a first polysilicon layer formed above the SOI substrate, an interlayer insulating film formed on the first polysilicon layer, and a second polysilicon layer formed on the interlayer insulating film.

Assignees

• Toshiba Kk

Inventors

• Kunishi Yugo
• Kuriyama Yasuhiko
• Itagaki Yoshio

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H01L23/538

  Electricity · mapped topic

• H01L29/94

  Electricity · mapped topic

• H03K17/005 Primary

  with several inputs only · CPC title