Method of manufacturing semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10121869-B2
Application number	US-201715832733-A
Country	US
Kind code	B2
Filing date	Dec 5, 2017
Priority date	Aug 4, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor memory device comprising:
providing a substrate;
forming a plurality of gate structures and a plurality of dielectric caps, wherein the gate structures are formed on the substrate and each gate structure comprise a first gate and a first gate dielectric layer, the first gate dielectric layer disposed between the first gate and the substrate, and the dielectric caps are formed atop the gate structures respectively;
forming a first dielectric layer covering the dielectric caps and a plurality of sidewalls of the gate structures;
forming a second dielectric layer covering the first dielectric layer, wherein materials of both the first dielectric layer and the second dielectric layer are different;
partially removing the second dielectric layer to reveal a plurality of top parts of the first dielectric layer and to form a plurality of first spacing films;
forming a plurality of second gates on the substrate, wherein the second gates covering and contacting the first dielectric layer and a top edge of the first spacing film;
removing the dielectric caps to reveal the first gates; and
forming a plurality of drains and a plurality of sources in the substrate.

2. The method according to claim 1 , wherein partially removing the second dielectric layer comprises performing a plasma etching.

3. The method according to claim 1 , wherein removing the dielectric caps comprise performing a wet etching.

4. The method according to claim 1 , wherein the substrate, the first gate dielectric layer, and the first gate form a SONOS structure.

5. The method according to claim 1 , further comprising partially removing the first dielectric layer to reveal the dielectric caps after forming the second gates.

6. The method according to claim 1 , further comprising forming an electric isolating structure in the substrate before forming the gate structures and the dielectric caps.

Assignees

• United Microelectronics Corp

Inventors

• Liu Weichang
• Chen Zhen
• Wang Shen-De
• Xiang Wang
• Ta Wei

Classifications

• H01L27/11568

  Electricity · mapped topic

• H01L29/792

  Electricity · mapped topic

• H01L29/42344 Primary

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic