Solid state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-10121807-B2
Application number	US-201715626567-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Nov 30, 2009
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.

First claim

What is claimed is:

1. A solid state imaging device, comprising:
a plurality of transistors including a reset transistor, an amplification transistor, a selection transistor, and a transfer transistor;
a plurality of transfer wiring lines, wherein the transfer transistor is connected to at least one of the plurality of transfer wiring lines, and wherein the plurality of transfer wiring lines are arranged parallel to one another in a plan view; and
a plurality of vertical signal lines, wherein the selection transistor is connected to at least one of the plurality of vertical signal lines, and wherein the plurality of vertical signal lines are arranged parallel to one another in the plan view, and wherein the plurality of vertical signal lines are arranged perpendicular to the plurality of transfer wiring lines in the plan view,
wherein the amplification transistor, the reset transistor, the selection transistor and the amplification transistor are disposed between the vertical signal lines in the plan view.

2. The solid state imaging device of claim 1 , further comprising shield wiring lines disposed between the plurality of transfer wiring lines, wherein the shield wiring lines are disposed to extend along a same direction as the plurality of transfer wiring lines in the plan view, wherein a potential of the shield wiring lines is a constant potential or a floating potential.

3. The solid state imaging device of claim 1 , wherein a gate electrode of the selection transistor and a gate electrode of the amplification transistor are disposed along a same direction as the plurality of transfer wiring lines in the plan view.

4. The solid state imaging device of claim 1 , wherein a gate electrode of the reset transistor is configured to receive a reset pulse via a reset wiring line.

5. The solid state imaging device of claim 1 , wherein a drain electrode of the reset transistor and a drain electrode of the amplification transistor are configured to receive different voltages.

6. The solid state imaging device of claim 1 , wherein a drain electrode of the reset transistor and a drain electrode of the amplification transistor are configured to receive a same voltage.

7. The solid state imaging device of claim 1 , further comprising a floating diffusion, wherein the transfer transistor is coupled to the floating diffusion, wherein the floating diffusion is disposed between the vertical signal lines in the plan view.

Assignees

• Sony Corp

Inventors

• Wakano Toshifumi
• Koga Fumihiko

Classifications

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H01L27/14636

  Electricity · mapped topic

• H01L27/14812

  Electricity · mapped topic

• H01L27/14612 Primary

  Electricity · mapped topic

• H01L27/14656

  Electricity · mapped topic