Solid state imaging device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9590007-B2
Application number	US-201615079168-A
Country	US
Kind code	B2
Filing date	Mar 24, 2016
Priority date	Nov 30, 2009
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.

First claim

What is claimed is:

1. An imaging device, comprising:
a semiconductor substrate including a plurality of photoelectric conversion portions,
wherein the plurality of photoelectric conversion portions are arranged to share at least a floating diffusion, a reset transistor electrically connected to the floating diffusion, and an amplification transistor electrically connected to the floating diffusion;
a first transfer transistor electrically connected to a first photoelectric conversion portion of the plurality of photoelectric conversion portions; and
a plurality of metal layers disposed at a side of the semiconductor substrate opposite a light-incident side of the semiconductor substrate, wherein the plurality of metal layers includes:
a first transfer wiring line electrically connected to a gate electrode of the first transfer transistor and disposed to extend in a horizontal direction;
a reset wiring line electrically connected to a gate electrode of the reset transistor and disposed in parallel to the first transfer wiring line, wherein the reset wiring line is disposed in a same layer of the plurality of metal layers as the first transfer wiring line; and
a well contact wiring line electrically connected to a well contact, wherein the well contact wiring line is configured to apply a well contact voltage to a semiconductor well area of the imaging device, wherein the well contact wiring line is disposed to extend, at least in part, in the horizontal direction, wherein the well contact wiring line is disposed, at least in part, to extend in the horizontal direction in a different layer than the first transfer wiring line.

2. The imaging device of claim 1 , wherein the gate electrode of the reset transistor is configured to receive a reset pulse via the reset wiring line.

3. The imaging device of claim 1 , wherein the first transfer wiring line is arranged to overlap a part of the first photoelectric conversion portion.

4. The imaging device of claim 1 , wherein the plurality of photoelectric conversion portions are further arranged to share a select transistor electrically connected to the amplification transistor.

5. The imaging device of claim 4 , wherein the plurality of metal layers further includes:
a row selection wiring line electrically connected to a gate electrode of the select transistor and disposed parallel to the first transfer wiring line in the same layer of the plurality of metal layers as the first transfer wiring line.

6. The imaging device of claim 4 , wherein the plurality of metal layers further includes a vertical signal line electrically connected to the select transistor.

7. The imaging device of claim 6 , wherein the vertical signal line is disposed to extend in a vertical direction in a different layer of the plurality of metal layers than the first transfer wiring line.

8. The imaging device of claim 4 , wherein a gate electrode of the select transistor and a gate electrode of the amplification transistor are disposed along the horizontal direction.

9. The imaging device of claim 1 , wherein a drain electrode of the reset transistor and a drain electrode of the amplification transistor are configured to receive different voltages.

10. The imaging device of claim 1 , further comprising a second transfer transistor electrically connected to a second photoelectric conversion portion of the plurality of photoelectric conversion portions,
wherein the plurality of metal layers further includes a second transfer wiring line disposed parallel to the first transfer wiring line in the same layer as the first transfer wiring line, wherein the second transfer wiring line is electrically connected to a gate electrode of the second transfer transistor.

11. The imaging device of claim 10 , wherein the second transfer wiring line is disposed to overlap a part of the second photoelectric conversion portion.

12. The imaging device of claim 10 , further comprising a third transfer transistor electrically connected to a third photoelectric conversion portion,
wherein the plurality of metal layers further includes a third transfer wiring line disposed parallel to the first transfer wiring line in the same layer as the first transfer wiring line, wherein the third transfer wiring line is electrically connected to a gate electrode of the third transfer transistor,
and wherein the second transfer wiring line, the third transfer wiring line, and the reset wiring line are disposed in order in a vertical direction.

13. The imaging device of claim 12 , wherein the second transfer wiring line, the third transfer wiring line, and the reset wiring line are disposed at substantially even intervals in the vertical direction.

14. An electronic apparatus, comprising:
a semiconductor substrate including a plurality of photoelectric conversion portions,
wherein the plurality of photoelectric conversion portions are arranged to share at least a floating diffusion, a reset transistor electrically connected to the floating diffusion, and an amplification transistor electrically connected to the floating diffusion;
a first transfer transistor electrically connected to a first photoelectric conversion portion of the plurality of photoelectric conversion portions; and
a plurality of metal layers disposed at a side of the semiconductor substrate opposite a light-incident side of the semiconductor substrate, wherein the plurality of metal layers includes:
a first transfer wiring line electrically connected to a gate electrode of the first transfer transistor and disposed to extend in a horizontal direction;
a reset wiring line electrically connected to a gate electrode of the reset transistor and disposed in parallel to the first transfer wiring line, wherein the reset wiring line is disposed in a same layer of the plurality of metal layers as the first transfer wiring line; and
a well contact wiring line electrically connected to a well contact, wherein the well contact wiring line is configured to apply a well contact voltage to a semiconductor well area of the imaging device, wherein the well contact wiring line is disposed to extend, at least in part, in the horizontal direction, wherein the well contact wiring line is disposed, at least in part, to extend in the horizontal direction in a different layer than the first transfer wiring line.

15. The electronic apparatus of claim 14 , wherein the gate electrode of the reset transistor is configured to receive a reset pulse via the reset wiring line.

16. The electronic apparatus of claim 14 , wherein the first transfer wiring line is arranged to overlap a part of the first photoelectric conversion portion.

17. The electronic apparatus of claim 14 , wherein the plurality of photoelectric conversion portions are further arranged to share a select transistor electrically connected to the amplification transistor.

18. The electronic apparatus of claim 17 , wherein the plurality of metal layers further includes:
a row selection wiring line electrically connected to a gate electrode of the select transistor and disposed parallel to the first transfer wiring line in the same layer of the plurality of metal layers as the first transfer wiring line.

19. The electronic apparatus of claim 17 , wherein the plurality of metal layers further includes a vertical signal line electrically connected to the select transistor.

20. The electronic apparatus of claim 19 , wherein the vertical signal line is disposed to extend in a vertical direction in a different layer of the plurali

Assignees

• Sony Corp

Inventors

• Wakano Toshifumi
• Koga Fumihiko

Classifications

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H01L27/14887

  Electricity · mapped topic

• H01L27/14812 Primary

  Electricity · mapped topic

• H10F39/1865

  Overflow drain structures · CPC title