Contact structure and extension formation for III-V nFET

Patent metadata

Field	Value
Publication number	US-10121703-B2
Application number	US-201715789972-A
Country	US
Kind code	B2
Filing date	Oct 21, 2017
Priority date	May 21, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

First claim

What is claimed is:

1. A method of fabricating fin-type field-effect transistors, comprising:
obtaining a semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers;
epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
forming n-type source/drain regions from the silicon-based semiconductor layer,
wherein epitaxially growing the silicon-based semiconductor layer further includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and having a top surface entirely beneath the portions of the III-V fin structures comprising each column and a second, undoped silicon layer on the first, p-type silicon layer, the n-type source/drain regions being formed from the second, undoped silicon layer subsequent to the first annealing process, and
further wherein forming n-type source/drain regions from the silicon-based semiconductor layer includes implanting dopant ions within the second, undoped silicon layer and subjecting the columns and the silicon-based semiconductor layer to a second annealing process subsequent to the first annealing process, thereby causing the second, undoped silicon layer to recrystallize following ion implantation.

2. The method of claim 1 , further including:
growing a III-V semi-isolating layer on the first III-V blanket layer,
forming the second III-V blanket layer on the III-V semi-isolating layer, and
forming the plurality of recess through the III-V semi-isolating layer, wherein the III-V base of each column includes a portion of the semi-isolating III-V layer adjoining one of the portions of the III-V fin structures.

3. The method of claim 2 , further including forming local isolation regions on the semi-isolating layer of III-V material.

4. The method of claim 1 , wherein the semiconductor substrate consists essentially of mono-crystalline silicon.

5. The method of claim 4 , wherein epitaxially growing the silicon-based semiconductor layer includes using silane as a source gas.

6. The method of claim 1 , wherein forming the n-type source/drain regions includes implanting the silicon-based semiconductor layer with arsenic or phosphorus ions subsequent to the first annealing process and followed by a second annealing process causing recrystallization of the silicon-based semiconductor layer.

7. The method of claim 6 , wherein epitaxially growing the silicon-based semiconductor layer includes using silane as a source gas.

8. The method of claim 7 , wherein the III-V fin structures comprise arsenic, and further causing arsenic from the III-V fin structures to be diffused into the silicon-based semiconductor layer during the first annealing process.

9. A method of fabricating fin-type field-effect transistors, comprising:
obtaining a semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portions of the III-V fin structures comprising the columns including top surfaces;
epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
forming n-type source/drain regions from the silicon-based semiconductor layer,
wherein epitaxially growing the silicon-based semiconductor layer further includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and a second, undoped silicon layer on the first, p-type silicon layer, the second, undoped silicon layer being epitaxially grown to or above the top surfaces of the portions of the III-V fin structures, the n-type source/drain regions being formed from the second, undoped silicon layer subsequent to the first annealing process, and
further wherein forming n-type source/drain regions from the silicon-based semiconductor layer includes implanting dopant ions within the second, undoped silicon layer and subjecting the columns and the silicon-based semiconductor layer to a second annealing process subsequent to the first annealing process, thereby causing the second, undoped silicon layer to recrystallize following ion implantation.

10. A method of fabricating fin-type field-effect transistors, comprising:
obtaining a semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
growing a III-V semi-isolating layer on the first III-V blanket layer;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer and on the III-V semi-isolating layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses through the first III-V blanket layer, the III-V semi-isolating layer, and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of the semi-isolating III-V layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portion of the semi-isolating III-V layer of each column adjoining the portion of the III-V fin structure of each column;
forming local isolation regions of III-V material on the s

Assignees

• IBM

Inventors

• Basker Veeraraghavan S
• Reznicek Alexander

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P95/408

  of Group III-V semiconductors, e.g. to render them semi-insulating · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/174

  being Group III-V material · CPC title