Configurable mailbox data buffer apparatus

Patent metadata

Field	Value
Publication number	US-10120815-B2
Application number	US-201615184789-A
Country	US
Kind code	B2
Filing date	Jun 16, 2016
Priority date	Jun 18, 2015
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

First claim

The invention claimed is:

1. A single chip microcontroller comprising a master core and a slave core, wherein the master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively, further comprising a communication interface between the master microcontroller and the slave microcontroller, wherein the communication interface comprises a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers, and further comprising fuses or configuration registers to configure each directional data registers.

2. The single chip microcontroller according to claim 1 , wherein each directional data register is configured by said fuses.

3. The single chip microcontroller according to claim 1 , wherein each directional data register is configured by said configuration register.

4. The single chip microcontroller according to claim 1 , further comprising handshake logic block configured to provide handshake signals between the master and slave core with respect to the plurality of configurable directional data registers.

5. The single chip microcontroller according to claim 1 , wherein the communication interface is further configurable to define a plurality of mailboxes, wherein a configurable number of consecutive data registers of said plurality of configurable data registers is assigned to each mailbox.

6. The single chip microcontroller according to claim 5 , further comprising fuses to configure each directional data registers.

7. The single chip microcontroller according to claim 5 , further comprising configuration registers to configure each directional data registers.

8. The single chip microcontroller according to claim 5 , wherein assignment of registers to a mailbox and a data direction of each of the plurality of configurable data register is programmed during programming of the single chip microcontroller.

9. The single chip microcontroller according to claim 5 , wherein one of said configurable registers of a mailbox is used as a control register.

10. The single chip microcontroller according to claim 1 , wherein a data direction of a configurable data register is assigned during programming of the single chip microcontroller.

11. The single chip microcontroller according to claim 1 , wherein each data register is controlled by a direction signal and a handshake signal.

12. The single chip microcontroller according to claim 1 , wherein at least one of said plurality of configurable data registers is as a status register.

13. The single chip microcontroller according to claim 1 , wherein at least one of said plurality of configurable data registers is as a command register.

14. The single chip microcontroller according to claim 1 , comprising a plurality of multiplexers for defining either a write path only from the master core to one of the configurable data register and a read path from the one of the configurable data register to the salve core or a write path only from the slave core to one of the configurable data register and a read path from the one of the configurable data register to the master core.

15. The single chip microcontroller according to claim 14 , wherein when the write path from the master or slave core to one of the configurable data register is set, respectively, a read path from the one of the configurable data register to the master or slave core is available.

16. The single chip microcontroller according to claim 14 , wherein when the write path from the master core to one of the configurable data register is set, the master clock provides a clock for writing the one of the configurable data register and the slave clock provides a clock for reading the one of the configurable data register.

17. The single chip microcontroller according to claim 14 , wherein when the write path from the slave core to one of the configurable data register is set, the slave clock provides a clock for writing the one of the configurable data register and the master clock provides a clock for reading the one of the configurable data register.

18. The single chip microcontroller according to claim 1 , further comprising a read FIFO memory and a write FIFO memory within the communication interface, wherein the read FIFO memory comprises a data input coupled with the slave core and a data output coupled with the master core and the write FIFO memory comprises a data input coupled with the master core and a data output coupled with the slave core.

19. The single chip microcontroller according to claim 18 , wherein the read FIFO memory and write FIFO memory are optionally enabled through a configuration register.

20. The single chip microcontroller according to claim 1 , further comprising a plurality of slave cores, wherein the communication interface comprises a plurality of data registers sets, each data register set comprising a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assigned a direction to each of the plurality of configurable data registers.

21. A method for providing communication between a master core and a slave core on a single chip microcontroller, wherein the master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively, the method comprising:
providing a communication interface between the master microcontroller and the slave microcontroller,
configuring a plurality of configurable directional data registers coupled with a flow control logic to form respective mailboxes by setting fuses or by programming configuration registers,
configuring for each of the plurality of configurable directional data registers a data direction from or to the master core;
exchanging data between the master core and the slave core only through said plurality of configurable directional data registers.

22. The method according to claim 21 , the steps of configuring is performed through fuses during programming of the single chip microcontroller.

23. The method according to claim 21 , wherein the step of exchanging is performed with handshake signals between the master and slave core.

24. The method according to claim 21 , wherein a configurable number of consecutive data registers of said plurality of configurable data registers is assigned to each mailbox.

25. The method according to claim 24 , wherein one of said configurable registers of a mailbox is used as a control register.

26. The method according to claim 24 , wherein at least one of said plurality of configurable data registers is as a status register or a command register.

Assignees

• Microchip Tech Inc

Inventors

• Catherwood Michael
• Mickey David
• Kris Bryan

Classifications

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F13/20

  for access to input/output bus · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F15/167 Primary

  using a common memory, e.g. mailbox · CPC title