Membrane transducer structures and methods of manufacturing same using thin-film encapsulation

US10118820B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10118820-B2
Application numberUS-201715469393-A
CountryUS
Kind codeB2
Filing dateMar 24, 2017
Priority dateJul 25, 2014
Publication dateNov 6, 2018
Grant dateNov 6, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Membrane transducer structures and thin-film encapsulation methods for manufacturing the same are provided. In one example, the thin film encapsulation methods may be implemented to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) that include the membrane transducers.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a microshell membrane transducer structure, comprising: providing a MEMS region over a substrate, the MEMS region including a MEMS structural layer defining at least one lower transducer capacitor plate over a MEMS sacrificial release layer; forming a first sacrificial layer over the lower transducer capacitor plate; forming a second sacrificial layer over and in contact with the first sacrificial layer, and then removing a part of the second sacrificial layer over at least a portion of the lower transducer capacitor plate so as to leave only the first sacrificial layer disposed over the portion of the lower transducer capacitor plate with no second sacrificial layer disposed over the portion of the lower transducer capacitor plate; forming an upper microshell layer over the first sacrificial layer and lower transducer capacitor plate; creating one or more upper release holes in the upper microshell layer; and removing the first sacrificial layer disposed over the portion of the lower transducer capacitor plate through the upper release holes to form an open area between the upper microshell layer and the lower transducer capacitor plate such that a portion of the upper microshell layer forms a transducer membrane disposed over the open area and underlying lower transducer capacitor plate. 2. The method of claim 1 , further comprising removing the MEMS sacrificial release layer beneath the lower transducer capacitor plate through the upper release holes to release the lower transducer capacitor plate following the step of removing the first sacrificial layer disposed over the portion of the lower transducer capacitor plate through the upper release holes. 3. The method of claim 1 , further comprising forming a sealing layer on the upper microshell layer to seal the upper release holes in the upper microshell layer following the step of removing the first sacrificial layer disposed over the portion of the lower transducer capacitor plate through the upper release holes. 4. The method of claim 3 , further comprising removing a portion of the sealing layer to form a transducer opening above the transducer membrane that exposes an upper surface of the transducer membrane to an ambient environment. 5. The method of claim 1 , further comprising providing an integrated circuit (IC) region between the MEMS region and the underlying substrate, the IC region including integrated circuitry; forming multiple conductive vias extending between the MEMS structural layer and the integrated circuitry of the IC region; forming one or more lower transducer contacts that electrically couple the lower transducer capacitor plate to a first portion of the integrated circuitry of the IC region through one or more of the conductive vias; and forming one or more membrane transducer contacts that electrically couple the membrane transducer to a second portion of the integrated circuitry of the IC region through one or more of the conductive vias. 6. The method of claim 1 , where the flexible portion of the upper micro shell layer further comprises one or more out-of-plane decoupling structures disposed around an in-plane central portion of the flexible transducer membrane, an open area defined under each of the out-of-plane decoupling structures that is contiguous with a cavity or open area defined between the in-plane central portion of the flexible transducer membrane and the lower transducer capacitor plate. 7. The method of claim 6 , where the out-of-plane decoupling structures comprise upwardly extending hinge structures. 8. The method of claim 1 , where the flexible portion of the upper microshell layer is configured to flex closer and further away from lower transducer capacitor plate due to external stimulus. 9. The method of claim 8 , where the external stimulus comprises varying pressure. 10. The method of claim 4 , further comprising forming the transducer opening in the sealing layer above the flexible transducer membrane in an aligned position over the flexible transducer membrane.

Assignees

Inventors

Classifications

  • MEMS characterised by an electronic circuit specially adapted for controlling or driving the same (B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00) · CPC title

  • Biosensors; Chemical sensors · CPC title

  • Releasing structures at the end of the manufacturing process · CPC title

  • Sensors changing capacitance upon adsorption or absorption of fluid components, e.g. electrolyte-insulator-semiconductor sensors, MOS capacitors (G01N27/225 takes precedence) · CPC title

  • Electricity · mapped topic

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What does patent US10118820B2 cover?
Membrane transducer structures and thin-film encapsulation methods for manufacturing the same are provided. In one example, the thin film encapsulation methods may be implemented to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) that include the membrane transducers.
Who is the assignee on this patent?
Semiconductor Mfg Int Shanghai Corp
What technology area does this patent fall under?
Primary CPC classification B81C1/00246. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Nov 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).