Manufacturing method of package substrate with metal on conductive portions

Patent metadata

Field	Value
Publication number	US-10117340-B2
Application number	US-201815973522-A
Country	US
Kind code	B2
Filing date	May 7, 2018
Priority date	Jul 29, 2015
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A manufacturing method of a package substrate includes forming a patterned first dielectric layer on a carrier; forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing one of the openings of the first dielectric layer, and the carrier in one of the openings; forming a first conductive pillar layer on the first wiring layer on the first surface; forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer; forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; forming an electrical pad layer on the second wiring layer; and forming a third dielectric layer on the second dielectric layer and the second wiring layer.

First claim

What is claimed is:

1. A manufacturing method of a package substrate, comprising:
(a) forming a patterned first dielectric layer on a carrier, such that the first dielectric layer has a plurality of openings;
(b) forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing at least one of the openings, and the carrier in at least one of the openings;
(c) forming a first conductive pillar layer on a portion of the first wiring layer that is on the first surface;
(d) forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer;
(e) forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer;
(f) forming an electrical pad layer on the second wiring layer; and
(g) forming a third dielectric layer on the second dielectric layer and the second wiring layer, wherein the electrical pad layer is exposed from the third dielectric layer.

2. The manufacturing method of the package substrate of claim 1 , wherein the first dielectric layer has a second surface opposite to the first surface, and the manufacturing method further comprises:
etching the carrier, thereby exposing the second surface and a portion of the first wiring layer that is on an end of the wall surface adjacent to the second surface.

3. The manufacturing method of the package substrate of claim 2 , further comprising:
cutting off the etched carrier and edges of the first, second, and third dielectric layers.

4. The manufacturing method of the package substrate of claim 1 , wherein step (d) comprises:
covering the first surface, the first wiring layer, the openings, and the first conductive pillar layer with the second dielectric layer; and
grinding the second dielectric layer, thereby exposing the first conductive pillar layer.

5. A manufacturing method of a package substrate, comprising:
(a) forming a patterned first dielectric layer on a carrier, such that the first dielectric layer has a plurality of openings;
(b) forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing at least one of the openings, and the carrier in at least one of the openings;
(c) forming a first conductive pillar layer on a portion of the first wiring layer that is on the first surface;
(d) forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer;
(e) forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer;
(f) forming a second conductive pillar layer on the second wiring layer; and
(g) forming a third dielectric layer on the second dielectric layer and the second wiring layer, wherein the second conductive pillar layer is exposed from the third dielectric layer.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Che-Wei
• Hsu Shih-Ping
• Chou Pao-Hung

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title