Reverse current protection circuit

Patent metadata

Field	Value
Publication number	US-10116291-B2
Application number	US-201615232521-A
Country	US
Kind code	B2
Filing date	Aug 9, 2016
Priority date	Aug 10, 2015
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

In described examples, a power interface subsystem includes power transistors, each having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal. A differential amplifier has: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node. An offset voltage source is coupled to cause an offset of a selected polarity at one of the inputs to the differential amplifier. The offset has a first polarity in a first operating mode and a second polarity in a second operating mode. Gate control circuitry is coupled to apply a control level at the control terminal(s) of selected one(s) of the power transistors responsive to a voltage at the output node, and to apply an off-state control level to the control terminal(s) of unselected one(s) of the power transistors.

First claim

What is claimed is:

1. A power interface subsystem for a battery-powered electronic system, comprising:
a power transistor having: a source/drain path coupled between a battery terminal and an accessory terminal; and a gate; and
a reverse current protection circuit including:
an input differential amplifier stage, including first and second input legs, the first leg coupled to the battery terminal, the second leg coupled to the accessory terminal, the first leg including first and second transistors with their source/drain paths connected in series, the second leg including third and fourth transistors with their source/drain paths connected in series, and the first and third transistors having gates connected together at the drain of the second transistor;
first and second load devices coupled to the first and second input legs, respectively;
an offset voltage source, coupled to the input differential amplifier stage to cause an offset of a selected polarity between the first and second input legs;
a replica bias leg including: a replica load device; and first and second replica transistors having their source/drain paths connected in series between the battery terminal and the replica load device, the drain of the second replica transistor connected to gates of the first and second replica transistors and to gates of the second and fourth transistors; and
gate control circuitry coupled to apply a gate voltage to the power transistor responsive to a voltage at an output node at the second load device.

2. The subsystem of claim 1 , wherein the reverse current protection circuit includes:
a clamp circuit coupled to clamp a voltage differential between the drain of the first transistor and the gates of the second and fourth transistors, and between the drain of the first replica transistor and the gates of the second and fourth transistors.

3. The subsystem of claim 2 , wherein the clamp circuit includes:
first and second clamp transistors having their source/drain paths connected in series between the drain of the first transistor and the gates of the second and fourth transistors, and having their gates connected to their respective drains; and
third and fourth clamp transistors having their source/drain paths connected in series between the drain of the first replica transistor and the gates of the second and fourth transistors, and having their gates connected to their respective drains.

4. The subsystem of claim 3 , wherein the power transistor is a high-voltage metal-oxide-semiconductor (MOS) transistor, and wherein the second and fourth transistors are low-voltage MOS transistors.

5. The subsystem of claim 1 , wherein the reverse current protection circuit includes:
a first resistor connected in series between the battery terminal and the first input leg;
a second resistor connected in series between the accessory terminal and the second input leg; and
a replica resistor connected in series between the battery terminal and the replica bias leg;
wherein the offset voltage source is coupled to the second input leg at a node between the second resistor and the source/drain path of the third transistor.

6. The subsystem of claim 5 , further comprising:
control circuitry coupled to control the offset voltage source to cause an offset of a first polarity between the first and second input legs in a first operating mode, and to cause an offset of a second polarity between the first and second input legs in a second operating mode.

7. The subsystem of claim 6 , further comprising:
an output diode connected at the output node; and
an output mode transistor having a source/drain path connected between the output diode and a reference voltage, and having a gate controlled by the control circuitry, so the output mode transistor is coupled to be turned on in the first operating mode and turned off in the second operating mode.

8. The subsystem of claim 7 , wherein the power transistor is a first power transistor, and the subsystem further comprises:
a second power transistor having a source/drain path coupled between the battery terminal and the accessory terminal, and having a gate coupled to the gate control circuitry, the second power transistor having a different on-state resistance than the first power transistor;
wherein the gate control circuitry is coupled to apply a gate voltage, responsive to the voltage at the output node, to a selected one of the first and second power transistors; and
wherein the gate control circuitry is coupled to apply an off-state gate voltage to an unselected one of the first and second power transistors.

9. The subsystem of claim 1 , wherein the power transistor is a first power transistor, and the subsystem further comprises:
a second power transistor having a source/drain path coupled between the battery terminal and the accessory terminal, and having a gate coupled to the gate control circuitry, the second power transistor having a different on-state resistance than the first power transistor;
wherein the gate control circuitry is coupled to apply a gate voltage responsive to the voltage at the output node to a selected one of the first and second power transistors; and
wherein the gate control circuitry is coupled to apply an off-state gate voltage to an unselected one of the first and second power transistors.

10. The subsystem of claim 1 , further comprising:
a power pass transistor having: a source/drain path connected in series with the source/drain path of the power transistor between the battery terminal and the accessory terminal; and a gate; and
a current sense and limit circuit having a first input coupled to the battery terminal and a second input coupled at an intermediate node between the source/drain paths of the power pass transistor and the power transistor, and having an output coupled to the gate of the power pass transistor, and coupled to control a state of the power pass transistor responsive to voltages at the battery terminal and the intermediate node.

11. A power interface subsystem for a battery-powered electronic system, comprising:
a power transistor having: a conduction path coupled between a battery terminal and an accessory terminal; and a control terminal; and
a reverse current protection circuit including:
a differential amplifier having: a first input coupled to the battery terminal; a second input coupled to the accessory terminal; and an output node;
an offset voltage source coupled to cause an offset of a selected polarity at inputs to the differential amplifier, the offset having a first polarity in a first operating mode and a second polarity in a second operating mode;
gate control circuitry coupled to apply a control level at the control terminal of the power transistor responsive to a voltage at the output node;
an output diode connected at the output node; and
an output mode transistor having: a conduction path connected between the output diode and a reference voltage; and a control terminal coupled to turn the output mode transistor on in the first operating mode and off in the second operating mode.

12. The subsystem of claim 11 , further comprising:
control circuitry coupled to apply a mode signal indicating an active one of the first and second operating modes to the offset voltage source and to the control terminal of the output mode transistor.

13. The subsystem of claim 12 , wherein:
the power transistor is a metal-oxide-semiconductor (MOS) transistor, the conduction path of the power transistor is a source/drain path of the power transistor, the control terminal of the power transistor is a gate of the power transistor, and the c

Assignees

• Texas Instruments Inc

Inventors

• Manohar Sujan Kundapur
• Son Roland Karl
• Luebbe Juergen
• Yu Eddie W

Classifications

• H03K17/08122 Primary

  in field-effect transistor switches · CPC title

• H02H3/18

  responsive to reversal of direct current · CPC title

• H03K5/08 Primary

  by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30) · CPC title

• H02H3/08

  responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) · CPC title

• H02H3/087

  for DC applications · CPC title