Semiconductor device

Patent metadata

Field	Value
Publication number	US-9536828-B2
Application number	US-201214651643-A
Country	US
Kind code	B2
Filing date	Dec 19, 2012
Priority date	Dec 19, 2012
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

On a semiconductor substrate, coils CL 5 and CL 6 and pads PD 5 , PD 6 , and PD 7 are formed. The coil CL 5 and the coil CL 6 are electrically connected in series between the pad PD 5 and the pad PD 6 , and the pad PD 7 is electrically connected between the coil CL 5 and the coil CL 6 . The coil magnetically coupled to the coil CL 5 is formed just below the coil CL 5 , the coil magnetically coupled to the coil CL 6 is formed just below the coil CL 6 , and they are connected in series. When a current is flowed in the coils connected in series formed just below the coils CL 5 and CL 6 , directions of induction current flowing in the coils CL 5 and CL 6 are opposed to each other in the coils CL 5 and CL 6.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first coil, a second coil, a third coil, a fourth coil, a first pad, a second pad, and a third pad formed on the semiconductor substrate through an insulation film; and
a lead wiring for connecting the first coil and the third coil to the third pad, the lead wiring extending from a portion between the first coil and the third coil to the third pad, and a width of the lead wiring being greater than a wiring width of the first coil and the third coil,
wherein the first coil and the third coil are electrically connected in series between the first pad and the second pad,
the third pad is electrically connected between the first coil and the third coil,
the second coil and the fourth coil are electrically connected in series,
the first coil is arranged above the second coil,
the third coil is arranged above the fourth coil,
the first coil and the second coil are not connected by a conductor but are magnetically coupled to each other,
the third coil and the fourth coil are not connected by a conductor but are magnetically coupled to each other, and,
when a current is flowed in the second coil and the fourth coil connected in series, directions of induction currents flowing in the first coil and the third coil are opposed to each other in the first coil and the third coil.

2. The semiconductor device according to claim 1 ,
wherein, when a current is flowed in the second coil and the fourth coil connected in series, directions of the current flowing in the second coil and the fourth coil are opposed to each other.

3. The semiconductor device according to claim 2 ,
wherein the first pad is arranged inside the first coil, and
the second pad is arranged inside the third coil.

4. The semiconductor device according to claim 3 ,
wherein the third pad is arranged in a region except for a portion between the first coil and the third coil.

5. The semiconductor device according to claim 4 ,
wherein a distance between the first coil and the third coil is smaller than a side of the third pad.

6. The semiconductor device according to claim 5 ,
wherein a winding direction of the first coil and a winding direction of the third coil are the same as each other.

7. The semiconductor device according to claim 6 ,
wherein a winding direction of the second coil and a winding direction of the fourth coil are the same as each other.

8. The semiconductor device according to claim 1 ,
wherein the first coil and the third coil are formed in the same layer as each other, and
the second coil and the fourth coil are formed in the same layer as each other.

9. The semiconductor device according to claim 1 ,
wherein a first wiring extending so as to overlap with either one or both of the first coil and the third coil in a plan view is formed in a layer different from the first coil, the second coil, the third coil and the fourth coil, and the first wiring has a slit at a position overlapping with either one or both of the first coil and the third coil in a plan view.

10. The semiconductor device according to claim 9 ,
wherein the first wiring is formed in a lower layer than the second coil and the fourth coil.

11. A semiconductor device including a first semiconductor chip and a second semiconductor chip,
wherein the first semiconductor chip comprises:
a first coil, a second coil, a third coil, a fourth coil, a first pad, a second pad, and a third pad; and
a lead wiring for connecting the first coil and the third coil to the third pad, the lead wiring extending from a portion between the first coil and the third coil to the third pad, and a width of the lead wiring being greater than a wiring width of the first coil and the third coil,

the second semiconductor chip has a plurality of fourth pads,
the first coil and the third coil are electrically connected in series between the first pad and the second pad,
the third pad is electrically connected between the first coil and the third coil,
the second coil and the fourth coil are electrically connected in series,
within the first semiconductor chip, the first coil is arranged above the second coil, and the third coil is arranged above the fourth coil,
the first coil and the second coil are not connected by a conductor but are magnetically coupled to each other,
the third coil and the fourth coil are not connected by a conductor but are magnetically coupled to each other,
the first pad, the second pad and the third pad of the first semiconductor chip are electrically connected to the plurality of fourth pads of the second semiconductor chip through conductive connection members, respectively,
when a current is flowed in the second coil and the fourth coil connected in series, directions of induction currents flowing in the first coil and the third coil are opposed to each other in the first coil and the third coil.

12. The semiconductor device according to claim 11 ,
wherein the first semiconductor chip has a transmission circuit,
the second semiconductor chip has a reception circuit,
a signal transmitted form the transmission circuit of the first semiconductor chip is transmitted to the reception circuit of the second semiconductor chip through the first coil, the second coil, the third coil and the fourth coil.

13. The semiconductor device according to claim 12 ,
wherein, when a current is flowed in the second coil and the fourth coil connected in series, directions of currents flowing in the second coil and the fourth coil are opposed to each other.

14. The semiconductor device according to claim 13 ,
wherein the first pad is arranged inside the first coil, and
the second pad is arranged inside the third coil.

15. The semiconductor device according to claim 14 ,
wherein the third pad is arranged in a region except for a portion between the first coil and the third coil.

16. A semiconductor device comprising:
a semiconductor substrate; and
a first coil, a second coil, a third coil and a pad formed on the semiconductor substrate through an insulation layer; and
a lead wiring for connecting the first coil and the third coil to the pad, the lead wiring extending from a portion between the first coil and the third coil to the pad, and a width of the lead wiring being greater than a wiring width of the first coil and the third coil,
wherein the first coil is arranged above the second coil,
the first coil and the second coil are not connected by a conductor but are magnetically coupled to each other, and
a first wiring extending so as to overlap with the first coil in a plan view is formed in a layer different from the first coil and the second coil, and
the first wiring has a slit at a position overlapping with the first coil in a plan view.

17. The semiconductor device according to claim 16 ,
wherein a second wiring extending so as not to overlap with the first coil in a plan view is formed in a layer different from the first coil and the second coil, and
a slit is not formed in the second wiring.

18. The semiconductor device according to claim 16 ,
wherein the first wiring is formed in a lower layer than the second coil.

19. The semiconductor device according to claim 1 , wherein the first coil and the third coil are adjacent in a first direction, and the lead wiring extends in a second direction perpendicular to the first direction.

20. The semiconductor device according to claim 1 , wherein the first coil, the third coil, the

Assignees

• Renesas Electronics Corp

Inventors

• Uchida Shinichi
• Nagase Hirokazu
• Funaya Takuo

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07554

  changes in dispositions · CPC title