Erasable programmable non-volatile memory

Patent metadata

Field	Value
Publication number	US-10115682-B2
Application number	US-201715481889-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Apr 13, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

First claim

What is claimed is:

1. An erasable programmable non-volatile memory, comprising:
a first transistor comprising a select gate, a first doped region and a second doped region, wherein the select gate is connected with a word line, and the first doped region is connected with a source line;
a second transistor comprising the second doped region, a third doped region and a floating gate, wherein the third doped region is connected with a bit line, the first transistor and the second transistor are n-type transistors, and the first doped region, the second doped region and the third doped region are n-type doped regions;
an erase gate region connected with an erase line, wherein the floating gate is extended over and located near the erase gate region; and
a metal layer disposed over the floating gate and connected with the bit line;
wherein the first transistor and the second transistor are constructed in a p-well region, and the erasable programmable non-volatile memory further comprises a deep n-well region between the p-well region and a p-type substrate.

2. The erasable programmable non-volatile memory as claimed in claim 1 , wherein during a program cycle, a first voltage is provided to the p-well region and the source line, a program voltage is provided to the bit line and the erase line, and an on voltage is provided to the word line, so that plural electrons are injected into the floating gate.

3. The erasable programmable non-volatile memory as claimed in claim 1 , wherein during an erase cycle, a first voltage is provided to the p-well region, the source line and the bit line, an erase voltage is provided to the erase line, and an off voltage is provided to the word line, so that plural electrons are ejected from the floating gate.

4. The erasable programmable non-volatile memory as claimed in claim 1 , wherein during a read cycle, a first voltage is provided to the p-well region, the source line and the erase line, a read voltage is provided to the bit line, and an on voltage is provided to the word line, so that a read current flows to the source line.

5. The erasable programmable non-volatile memory as claimed in claim 1 , wherein a first part of the floating gate is disposed over and overlapped with the erase gate region, and a second part of the floating gate is disposed over and overlapped with a channel region of the second transistor, wherein a ratio of an area of the first part to an area of the second part is in a range between ¼ and ⅔.

6. The erasable programmable non-volatile memory as claimed in claim 1 , wherein an area of the metal layer is larger than an area of the floating gate.

7. An erasable programmable non-volatile memory, comprising:
a select transistor, wherein a gate terminal of the select transistor is connected with a word line, and a first drain/source terminal of the select transistor is connected with a source line;
a floating gate transistor, wherein a first drain/source terminal of the floating gate transistor is connected with a second drain/source terminal of the select transistor, and a second drain/source terminal of the floating gate transistor is connected with a bit line, wherein the floating gate transistor comprises a floating gate;
a first capacitor connected between the floating gate and an erase line; and
a second capacitor connected between the floating gate and the bit line.

8. The erasable programmable non-volatile memory as claimed in claim 7 , wherein the select transistor and the floating gate transistor are n-type transistors, and the select transistor and the floating gate transistor are constructed in a p-well region.

9. The erasable programmable non-volatile memory as claimed in claim 8 , wherein during a program cycle, a first voltage is provided to the p-well region and the source line, a program voltage is provided to the bit line and the erase line, and an on voltage is provided to the word line, so that plural hot carriers are injected into the floating gate.

10. The erasable programmable non-volatile memory as claimed in claim 8 , wherein during an erase cycle, a first voltage is provided to the p-well region, the source line and the bit line, an erase voltage is provided to the erase line, and an off voltage is provided to the word line, so that plural electrons are ejected from the floating gate.

11. The erasable programmable non-volatile memory as claimed in claim 8 , wherein during a read cycle, a first voltage is provided to the p-well region, the source line and the erase line, a read voltage is provided to the bit line, and an on voltage is provided to the word line, so that a read current flows to the source line.

Assignees

• Ememory Technology Inc

Inventors

• Li Chun-Hsiao
• Chen Wei-Ren
• Chen Hsueh-Wei

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• G11C16/0441

  comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates · CPC title

• G11C2216/10

  Floating gate memory cells with a single polysilicon layer · CPC title

• G11C16/10

  Programming or data input circuits · CPC title