Data-storage device and flash memory control method

Patent metadata

Field	Value
Publication number	US-9244833-B2
Application number	US-201313862816-A
Country	US
Kind code	B2
Filing date	Apr 15, 2013
Priority date	May 30, 2012
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

FLASH memory is allocated to provide a data-storage device and management tables. The management tables may record logical-to-physical address mapping information in a hierarchical structure consisting of at least two levels. Further, in addition to the logical-to-physical address mapping information, the management tables may further provide a valid page count table and an invalid block record. The logical-to-physical address mapping information is updated after an update of the valid page count table is completed. The invalid block record is maintained based on the valid page count table.

First claim

What is claimed is:

1. A data-storage device, comprising:
a FLASH memory, providing data-storage space and recorded with logical-to-physical address mapping information, wherein:
the logical-to-physical address mapping information includes a group table and a plurality of logical-to-physical address mapping tables corresponding to different groups;
each entry in the group table corresponds to one group and points to one logical-to-physical address mapping table corresponding thereto; and
the logical-to-physical address mapping tables show how host addresses are mapped to the data-storage space;
a controller, executing firmware to allocate the data-storage space to store data issued from a host and to maintain the logical-to-physical address mapping information in the FLASH memory; wherein
when allocating a first new page in the FLASH memory to update a target host page, the controller further corrects the physical-to-logical address mapping table in a random-access memory to record that the first new page maps to the target host page, copies an original page of the target host page from the FLASH memory to the random-access memory to be updated in the random-access memory and then write to the first new page of the FLASH memory in accordance with the physical-to-logical address mapping table provided by the random-access memory, allocates a second new page in the FLASH memory for update of the logical-to-physical address mapping table corresponding to the target host page to point to the first new page by one entry therein, and allocates a third new page in the FLASH memory for update of the group table to point to the second new page by one entry therein.

2. The data-storage device as claimed in claim 1 , wherein the FLASH memory comprises a plurality of blocks and each of the blocks comprises a plurality of pages.

3. The data-storage device as claimed in claim 2 , wherein each entry in the logical-to-physical address mapping table corresponds to a host page and is recorded with a block tag and a page tag indicating where the host page is stored in the data-storage space.

4. The data-storage device as claimed in claim 3 , wherein each entry in the group table is recorded with a block tag and a page tag indicating where the logical-to-physical address mapping table corresponding thereto is stored in the data-storage space.

5. The data-storage device as claimed in claim 4 , wherein
the random-access memory, records a physical-to-logical address mapping table according to the controller executing the firmware, to timely update a mapping showing how the pages of the FLASH memory are mapped to host pages.

6. A FLASH memory control method, comprising:
allocating data-storage space in a FLASH memory, to store data issued from a host; and
maintaining logical-to-physical address mapping information in the FLASH memory, wherein:
the logical-to-physical address mapping information includes a group table and a plurality of logical-to-physical address mapping tables corresponding to different groups;
each entry in the group table corresponds to one group and points to one logical-to-physical address mapping table corresponding thereto;
the logical-to-physical address mapping tables show how host addresses are mapped to the data-storage space;
allocating a first new page in the FLASH memory to update a target host page;
correcting the physical-to-logical address mapping table in the random-access memory to record that the first new page maps to the target host page;
copying an original page of the target host page from the FLASH memory to the random-access memory to be updated in the random-access memory and then write to the first new page of the FLASH memory in accordance with the physical-to-logical address mapping table provided by the random-access memory;
allocating a second new page in the FLASH memory for update of the logical-to-physical address mapping table corresponding to the target host page to point to the first new page by one entry therein; and
allocating a third new page in the FLASH memory for update of the group table to point to the second new page by one entry therein.

7. The FLASH memory control method as claimed in claim 6 , wherein the FLASH memory comprises a plurality of blocks and each of the blocks comprises a plurality of pages.

8. The FLASH memory control method as claimed in claim 7 , wherein each entry in the logical-to-physical address mapping table corresponds to a host page and is recorded with a block tag and a page tag indicating where the host page is stored in the data-storage space.

9. The FLASH memory control method as claimed in claim 8 , wherein each entry in the group table is recorded with a block tag and a page tag indicating where the logical-to-physical address mapping table corresponding thereto is stored in the data-storage space.

10. The FLASH memory control method as claimed in claim 9 , further comprising:
recording a physical-to-logical address mapping table in the random-access memory to timely update a mapping showing how the pages of the FLASH memory are mapped to host pages.

Assignees

• Silicon Motion Inc

Inventors

• Cheng Chang-Kai

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title