Back channel support for systems with split lane swap

US10114786B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10114786-B2
Application numberUS-201715795783-A
CountryUS
Kind codeB2
Filing dateOct 27, 2017
Priority dateJul 3, 2013
Publication dateOct 30, 2018
Grant dateOct 30, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Example embodiments may include a method for configuring an interface that includes determining information for a configuration of an interface of a first device including a plurality of SERDES slices having a plurality of connections to a second device over the interface; and configuring a back channel layer associated with the first device to form a back channel path to carry a message between a transmitter and a receiver of the first device based on the configuration of the plurality of connections to the second device. The transmitter can be in a first SERDES slice of the plurality of SERDES slices and the receiver is in a second SERDES slice of the plurality of SERDES slices.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: configuring a back channel layer to form a back channel path to carry a first message to a first transmitter from a first receiver, wherein the first transmitter is in a first serializer/deserializer (SERDES) slice of a plurality of SERDES slices, and the first SERDES slice is assigned a lane ID; receiving, at the first receiver, a second message, wherein the first receiver is in a second SERDES slice of a plurality of SERDES slices, and the back channel layer inserts a recipient ID in the second message to produce the first message; and determining, with an interface layer, whether the recipient ID in the first message matches the lane ID, wherein the interface layer interfaces to the first SERDES slice. 2. The method of claim 1 , wherein the back channel layer is associated with a first crossbar switch. 3. The method of claim 1 , further comprising tuning the first transmitter by receiving a command forwarded from the first receiver over the back channel path. 4. The method of claim 1 , wherein the first transmitter and the first receiver are coupled to a second receiver and a second transmitter, respectively, over the interface, the second receiver and the second transmitter being in a same SERDES slice, and the method further comprises receiving a message sent by the second transmitter over the interface at the first receiver, wherein the message sent by the second transmitter comprises a command message generated by the second receiver. 5. The method of claim 1 , wherein the configuring comprises configuring a back channel mapping layer to form the back channel path to carry messages between the first transmitter and the first receiver. 6. The method of claim 1 , wherein the configuring comprises configuring a back channel bus by assigning the recipient ID to the second SERDES slice, and the recipient ID identifies the first SERDES slice. 7. The method of claim 1 , wherein the configuring comprises configuring a daisy chain back channel bus. 8. An apparatus comprising: a first slice of a plurality of serializer/deserializer (SERDES) slices, wherein the first slice includes a first transmitter, and the first slice is assigned a lane ID 1 ; an interface layer that interfaces to the first slice, wherein the interface layer is configured to determine whether a recipient ID in a first message matches the lane ID; a second slice of the plurality of SERDES slices, wherein the second slice includes a first receiver configured to receive a second message; and a back channel layer configured to insert the recipient ID in the second message to produce the first message and to form a back channel path to carry the first message from the first receiver to the first transmitter. 9. The apparatus of claim 8 , wherein the back channel layer comprises a mapping layer. 10. The apparatus of claim 9 , wherein the mapping layer comprises a programmable multiplexing layer. 11. The apparatus of claim 8 , wherein the back channel layer comprises a daisy chain back channel bus. 12. The apparatus of claim 11 , wherein the daisy chain back channel bus comprises a plurality of interface layers coupled together in a daisy chain configuration, and each of the plurality of interface layers is coupled to a corresponding SERDES slice of the plurality of SERDES slices. 13. The apparatus of claim 12 , wherein each of the plurality of interface layers and the second slice are associated with a lane ID and a recipient ID. 14. The apparatus of claim 8 , wherein the apparatus comprises a first SERDES device and a second SERDES device, and the first transmitter and the first receiver are coupled to a second receiver and a second transmitter, respectively, of the second SERDES device over an interface, the second receiver and the second transmitter being in a same SERDES slice of the second SERDES device. 15. Non-transitory media encoded with logic that includes instructions for execution and, when executed by a processor, is operable to perform operations comprising: configuring a back channel layer to form a back channel path to carry a first message to a first transmitter from a first receiver, wherein the first transmitter is in a first serializer/deserializer (SERDES) slice of a plurality of SERDES slices, and the first SERDES slice is assigned a lane ID; receiving, at the first receiver, a second message, wherein the first receiver is in a second SERDES slice of the plurality of SERDES slices, and the back channel layer inserts a recipient ID in the second message to produce the first message; and determining, with an interface layer, whether the recipient ID in the first message matches the lane ID, wherein the interface layer interfaces to the first SERDES slice. 16. The media of claim 15 , wherein the operations further comprise tuning the first transmitter by receiving a command forwarded from the first receiver over the back channel path. 17. The media of claim 15 , wherein the first transmitter and the first receiver are coupled to a second receiver and a second transmitter, respectively, over the interface, the second receiver and the second transmitter being in a same SERDES slice, and the operations further comprises receiving a message sent by the second transmitter over the interface at the first receiver, wherein the message sent by the second transmitter comprises a command message generated by the second receiver. 18. The media of claim 15 , wherein the configuring comprises configuring a back channel mapping layer to form the back channel path to carry messages between the first transmitter and the first receiver. 19. The media of claim 1 , wherein the configuring comprises configuring a back channel bus by assigning the recipient ID to the second SERDES slice, and the recipient ID identifies the first SERDES slice. 20. The media of claim 1 , wherein the configuring comprises configuring a daisy chain back channel bus.

Assignees

Inventors

Classifications

  • using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing · CPC title

  • using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

  • H04L25/14Primary

    Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

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Frequently asked questions

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What does patent US10114786B2 cover?
Example embodiments may include a method for configuring an interface that includes determining information for a configuration of an interface of a first device including a plurality of SERDES slices having a plurality of connections to a second device over the interface; and configuring a back channel layer associated with the first device to form a back channel path to carry a message betwee…
Who is the assignee on this patent?
Cisco Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F13/4022. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 30 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).