System arbiter with programmable priority levels

Patent metadata

Field	Value
Publication number	US-10114776-B2
Application number	US-201715498846-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	Nov 3, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

First claim

What is claimed is:

1. An embedded controller comprising:
a system bus;
a central processing unit (“CPU”) communicatively coupled to the system bus, the central processing unit comprising a CPU priority register, and the central processing unit operable to access the system according to a plurality of operating modes;
a plurality of arbiter clients communicatively coupled to the system bus, each of the plurality of arbiter clients comprising a programmable priority register; and
a programmable system arbiter for granting access to the system bus among the plurality of arbiter clients and the central processing unit, the programmable system arbiter communicatively coupled to the plurality of arbiter clients and the system bus and the central processing unit, wherein:
the programmable system arbiter comprises one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and
the programmable system arbiter is operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of the plurality of operating modes, and each of the one or more interrupt types.

2. The embedded controller of claim 1 , wherein the plurality of operating modes comprises a stall mode.

3. The embedded controller of claim 1 , wherein the plurality of operating modes comprises a steal mode.

4. The embedded controller of claim 1 , wherein the plurality of arbiter clients comprises a direct memory access (“DMA”) channel.

5. The embedded controller of claim 1 , wherein the programmable system arbiter is further operable to protect the programmed priority order based at least on a LOCK/UNLOCK mechanism.

6. The embedded controller of claim 1 , wherein the programmable system arbiter further comprises a hardcoded priority table backup.

7. The embedded controller of claim 1 , wherein the programmed priority order is programmed in the programmable system arbiter during initialization of the embedded controller.

8. The embedded controller of claim 1 , wherein the programmed priority order is programmed in the programmable system arbiter during execution of program instructions stored in memory.

9. A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit, the programmable system arbiter comprising:
one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and
system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

10. The programmable system arbiter of claim 9 , wherein the plurality of operating modes comprises a stall mode.

11. The programmable system arbiter of claim 9 , wherein the plurality of operating modes comprises a steal mode.

12. The programmable system arbiter of claim 9 , wherein the plurality of arbiter clients comprises a direct memory access (“DMA”) channel.

13. The programmable system arbiter of claim 9 , wherein the programmable system arbiter is further operable to protect the programmed priority order based at least on a LOCK/UNLOCK mechanism.

14. The programmable system arbiter of claim 9 , wherein the programmable system arbiter further comprises a hardcoded priority table backup.

15. The programmable system arbiter of claim 9 , wherein the programmed priority order is programmed in the programmable system arbiter during initialization of the embedded controller.

16. The programmable system arbiter of claim 9 , wherein the programmed priority order is programmed in the programmable system arbiter during execution of program instructions stored in memory.

17. A method for providing system arbitration for an embedded controller comprising a system bus, a central processing unit, a plurality of arbiter clients, and a programmable system arbiter, the method comprising:
programming a priority level into a programmable priority register of an arbiter client for each of the plurality of arbiter clients;
programming a priority level into a central processing unit priority register of a central processing unit for each of a plurality of operating modes of the central processing unit;
programming a priority level into an interrupt priority register of the programmable system arbiter for each of a one or more interrupt types; and
programming a programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of the plurality of operating modes, and each of the one or more interrupt types.

18. The method of claim 17 , further comprising protecting the programmed priority order based at least on a LOCK/UNLOCK mechanism.

19. The method of claim 17 , wherein the programmed priority order is programmed in the programmable system arbiter during initialization of the embedded controller.

20. The method of claim 17 , wherein the programmed priority order is programmed in the programmable system arbiter during execution of program instructions stored in memory.

Assignees

• Microchip Tech Inc

Inventors

• Steedman Sean
• Kilzer Kevin
• Senapati Ashish
• Milks Justin
• Pulipaka Prashanth

Classifications

• G06F13/362 Primary

  with centralised access control · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/26

  with priority control · CPC title

• G06F13/34

  with priority control · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title