Real time analysis and control for a multiprocessor system

Patent metadata

Field	Value
Publication number	US-10114739-B2
Application number	US-201615276370-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Nov 9, 2012
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

System and method for testing a DUT that includes a multiprocessor array (MPA) executing application software at operational speed. The application software may be configured for deployment on first hardware resources of the MPA and may be analyzed. Testing code for configuring hardware resources on the MPA to duplicate data generated in the application software for testing purposes may be created. The application software may be deployed on the first hardware resources. Input data may be provided to stimulate the DUT. The testing code may be executed to provide at least a subset of first data to a pin at an edge of the MPA for analyzing the DUT using a hardware resource of the MPA not used in executing the application software. The first data may be generated in response to a send statement executed by the application software based on the input data.

First claim

What is claimed is:

1. A method, comprising:
analyzing application software;
developing test software based, at least in part, on results of analyzing the application software;
deploying the application software on a first hardware resource of a multi-processor array (MPA), wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes at least a first subset of the plurality of processing elements;
deploying the test software on a second hardware resource of the MPA, wherein the second hardware resource includes at least a second subset of the plurality of processing elements different than the first subset of the plurality of processing elements;
executing the application software on the first hardware resource; and
executing the test software on the second hardware resource, wherein executing the test software includes:
polling, by a first processing element included in the second hardware resource, one or more registers associated with a direct memory access (DMA) transfer in the first hardware resource resulting from executing one or more program commands included in the application software; and
sending, by the first processing element, auxiliary data retrieved from the one or more registers to a storage location for analysis, wherein an amount of auxiliary data is less than an amount of data generated by the application software; and
rebuilding the application software based on the auxiliary data.

2. The method of claim 1 , wherein a priority of the first processing element polling is less than a priority associated with performing the DMA in the first hardware resource.

3. The method of claim 1 , further comprising modifying the application software to include at least one probe command, and wherein executing the application software on the first hardware resource includes generating probe data in response to executing the at least one probe command.

4. The method of claim 3 , wherein executing the application software on the first hardware resource includes:
streaming, by a first DMA engine of a plurality of DMA engines, data resulting from executing the application software and the probe data to a particular memory of the plurality of memories; and
streaming, by a second DMA engine of the plurality of DMA engines, the data resulting from executing the application software to a target location in the plurality of memories.

5. The method of claim 4 , wherein executing the test software on the second hardware resource includes streaming, by a third DMA engine of the plurality of DMA engines, to the storage location for analysis.

6. The method of claim 5 , further comprising coordinating operation of the first, second, and third DMA engines.

7. A non-transitory computer-accessible storage medium having program instructions stored therein that, in response to execution by a multi-processor system, causes the multi-processor system to perform operation including:
analyzing application software;
developing test software based, at least in part, on results of analyzing the application software;
deploying the application software on a first hardware resource of a multi-processor array (MPA), wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes at least a first subset of the plurality of processing elements;
deploying the test software on a second hardware resource of the MPA, wherein the second hardware resource includes at least a second subset of the plurality of processing elements different than the first subset of the plurality of processing elements;
executing the application software on the first hardware resource; and
executing the test software on the second hardware resource, wherein executing the test software includes:
polling, by a first processing element included in the second hardware resource, one or more registers associated with a direct memory access (DMA) transfer in the first hardware resource resulting from executing one or more program commands included in the application software; and
sending, by the first processing element, auxiliary data retrieved from the one or more registers to a storage location for analysis, wherein an amount of auxiliary data is less than an amount of data generated by the application software; and
rebuilding the application software based on the auxiliary data.

8. The non-transitory computer-accessible storage medium of claim 7 , wherein a priority of the first processing element polling is less than a priority associated with performing the DMA in the first hardware resource.

9. The non-transitory computer-accessible storage medium of claim 7 , wherein the operations further include modifying the application software to include at least one probe command, and wherein executing the application software on the first hardware resource includes generating probe data in response to executing the at least one probe command.

10. The non-transitory computer-accessible storage medium of claim 9 , wherein executing the application software on the first hardware resource includes:
streaming, by a first DMA engine of a plurality of DMA engines, data resulting from executing the application software and the probe data to a particular memory of the plurality of memories; and
streaming, by a second DMA engine of the plurality of DMA engines, the data resulting from executing the application software to a target location in the plurality of memories.

11. The non-transitory computer-accessible storage medium of claim 10 , wherein executing the test software on the second hardware resource includes streaming, by a third DMA engine of the plurality of DMA engines, to the storage location for analysis.

12. The non-transitory computer-accessible storage medium of claim 11 , wherein the operations further include coordinating operation of the first, second, and third DMA engines.

13. The non-transitory computer-accessible storage medium of claim 11 , wherein the operations further include:
streaming, by the first DMA engine, the data resulting from executing the application software via a first one or more routes included in a set of routes defined for the application software;
streaming, by the second DMA engine, the data resulting from executing the application software via a second one or more routes included in the set of routes defined for the application software; and
streaming, by the third DMA engine, the probe data via a third one or more routes excluded from the set of routes defined for the application software.

14. A system, comprising:
one or more memories configured to store instructions;
one or more processors configured to receive instructions from the one or more memories and execute the instructions to cause the system to perform operations including:
analyzing application software;
developing test software based, at least in part, on results of analyzing the application software;
deploying the application software on a first hardware resource of a multi-processor array (MPA), wherein the MPA includes a plurality of processing elements, a plurality of memories, and an interconnection network communicatively coupling the plurality of processing elements to the plurality of memories, wherein the first hardware resource includes at least a first subset of the plurality of pr

Assignees

• Coherent Logix Inc

Inventors

• Ellis Geoffrey N
• Beardslee John Mark
• Doerr Michael B
• Aguayo Ivan
• Dalio Brian A

Classifications

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F11/3688 Primary

  for test execution, e.g. scheduling of test suites · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F9/45504

  Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators · CPC title