System and method for error detection of executed program code employing compressed instruction signatures

Patent metadata

Field	Value
Publication number	US-10114685-B2
Application number	US-201615014251-A
Country	US
Kind code	B2
Filing date	Feb 3, 2016
Priority date	Feb 5, 2015
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode. Moreover, the second processor is configured to determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

First claim

The invention claimed is:

1. A system, comprising:
a first processor configured to:
load from a first memory an instruction block comprising a plurality of opcodes and a stored error code;
for each opcode of the plurality of opcodes of the instruction block, determine a first determined signature depending on said opcode;
determine, for the instruction block, a determined error code which depends on each opcode and on the first determined signature of each opcode of the plurality of opcodes of the instruction block; and
determine that a first error occurred, if the determined error code is different from the stored error code; and

a second processor configured to:
determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode; and
determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode.

2. A system according to claim 1 , wherein the second processor is configured to execute the current opcode or a control signal depending on the current opcode, if the second determined signature for the current opcode is not different from the first determined signature for the current opcode.

3. A system according to claim 1 , wherein, for each opcode of the plurality of opcodes, the first processor is configured to:
decode said opcode to obtain a control signal for said opcode, the respective control signal being one of a plurality of control signals; and
determine the first determined signature of said opcode depending on the control signal of said opcode.

4. A system according to claim 3 , wherein the first processor comprises:
a first instruction decoder, wherein, for each opcode of the plurality of opcodes, the first instruction decoder is configured to decode said opcode to obtain the control signal for said opcode;
an error code generator configured to determine the determined error code for the instruction block using the control signal of each opcode of the plurality of opcodes of the instruction block; and
a first comparator configured to determine that the first error occurred, if the determined error code is different from the stored error code.

5. A system according to claim 3 , further comprising:
a second memory,
wherein, for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to store said opcode or the control signal depending on said opcode, and the first determined signature for said opcode, into the second memory, and
wherein the second processor is configured to load the current opcode or the control signal depending on the current opcode, and the first determined signature for the current opcode, from the second memory.

6. A system according to claim 5 , wherein the second memory is a cache.

7. A system according to claim 5 , wherein:
for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to store said opcode into the second memory, and
the second processor comprises:
a second instruction decoder configured to load the current opcode from the second memory, and decode the current opcode to obtain the control signal of the current opcode;
a first signature determiner configured to determine the second determined signature for the current opcode using the control signal of the current opcode;
a second comparator configured to:
load the first determined signature for the current opcode from the second memory; and
determine that the second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode; and

a first arithmetic logic.

8. A system according to claim 7 , wherein the second processor further comprises:
a second signature determiner configured to determine a third determined signature for the current opcode using the control signal of the current opcode;
a third comparator configured to determine that a third error occurred, if the third determined signature for the current opcode is different from the first determined signature for the current opcode; and
a second arithmetic logic is configured to execute the control signal of the current opcode, if the third determined signature for the current opcode is not different from the first determined signature for the current opcode.

9. A system according to claim 8 , further comprising:
an execution deviation detector configured to detect deviating results of the execution of the current opcode or of the execution of the control signal of the current opcode by the first arithmetic logic and by the second arithmetic logic.

10. A system according to claim 5 , wherein:
for each opcode of the plurality of opcodes of the instruction block, the first processor is configured to store the control signal for said opcode into the second memory;
the second processor comprises:
a first signature determiner configured to load the control signal of the current opcode from the second memory, and determine the second determined signature for the current opcode using the control signal of the current opcode;
a second comparator configured to:
load the first determined signature for the current opcode from the second memory; and
determine that the second error occurred, if the second determined signature for the current opcode is different from the first determined signature for the current opcode; and

a first arithmetic logic.

11. A system according to claim 1 ,
wherein the first processor is configured to:
for each opcode of the plurality of opcodes of the instruction block, determine the first determined signature depending on said opcode and depending on a first value for said opcode of a first program counter; and
determine a determined error code for the instruction block depending on each opcode of the plurality of opcodes of the instruction block and depending on the value of the first program counter for each opcode of the plurality of opcodes of the instruction block; and

wherein the second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode and depending on a second value for said opcode of a second program counter.

12. A system according to claim 1 ,
wherein the first processor is configured to determine, if the instruction block comprises a partial opcode, wherein said partial opcode is incomplete;
wherein, if the partial opcode is located at an end of the instruction block, the first processor is configured to load at least a first word of a first further instruction block to obtain a missing portion, missing in the partial opcode, and to determine the error code depending on the partial opcode and depending on the missing portion; and wherein, if the partial opcode is located at a start of the instruction block, the first processor is configured to determine the error code not depending on the partial opcode; or
wherein, if the partial opcode is located at the start of the instruction block, the first processor is configured to load at least a last word of a second further instruction block to obtain the missing portion, missing in the partial opcode, and to determine the error code depending on the partial opcode and the missing portion; and wherein, if the partial opcode is located at the end of the instruction block, the first processor is configured to determine the error code not depending on the partial opcode.

13. A system according to

Assignees

• Infineon Technologies Ag

Inventors

• Sonnekalb Steffen
• Wenzel Andreas

Classifications

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F2212/452

  Instruction code · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F11/0706

  the processing taking place on a specific hardware platform or in a specific software environment · CPC title

• G06F11/0721 Primary

  within a central processing unit [CPU] · CPC title