Hybrid memory controller with command buffer for arbitrating access to volatile and non-volatile memories in a hybrid memory group

Patent metadata

Field	Value
Publication number	US-10114560-B2
Application number	US-201715788501-A
Country	US
Kind code	B2
Filing date	Oct 19, 2017
Priority date	Mar 3, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

First claim

What is claimed is:

1. A hybrid memory controller for controlling a hybrid memory group comprising a volatile memory device and a non-volatile memory device, the hybrid memory controller comprising:
a processor; and
a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to perform:
receiving a first central processing unit (CPU) request to write to/read from the hybrid memory group;
identifying the volatile memory device as a first target of the first CPU request by decoding and address mapping of the first CPU request;
queuing the first CPU request in a buffer;
receiving a second CPU request to write to/read from the hybrid memory group;
identifying the non-volatile memory device as a second target of the second CPU request by decoding and address mapping of the second CPU request;
queuing the second CPU request in the buffer;
generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and, in response to generating the first command, generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets; and
transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

2. The hybrid memory controller of claim 1 , wherein the instructions further cause the processor to perform:
identifying the volatile and non-volatile memory devices by detecting an associated serial presence detect (SPD) data stored in each of the volatile and non-volatile memory devices.

3. The hybrid memory controller of claim 2 , wherein the identifying of the volatile and non-volatile memory devices occurs at a boot-up time.

4. The hybrid memory controller of claim 2 , wherein identifying the volatile and non-volatile memory devices comprises address mapping the volatile and non-volatile memory devices.

5. The hybrid memory controller of claim 2 , wherein the instructions further cause the processor to perform:
identifying timing parameters of the volatile and non-volatile memory devices based on the associated SPD data; and
determining the arbitration policy based on the timing parameters.

6. The hybrid memory controller of claim 2 , wherein the instructions further cause the processor to perform:
receiving a status feedback signal from the non-volatile memory device; and
determining the arbitration policy based on the status feedback signal.

7. The hybrid memory controller of claim 1 , wherein the arbitration policy comprises a round-robin arbitration policy or a weighted round-robin arbitration policy based on unbalanced issue speeds of the first and second queues.

8. The hybrid memory controller of claim 1 , wherein the non-volatile memory device and the volatile memory device are at different memory ranks of a same memory channel.

9. The hybrid memory controller of claim 1 , wherein the non-volatile memory device and the volatile memory device are at different memory banks of a same memory rank.

10. The hybrid memory controller of claim 1 , wherein the first and second queues are a same queue.

11. The hybrid memory controller of claim 1 , wherein the first and second commands are generated according to a same standard volatile memory command set.

12. The hybrid memory controller of claim 1 , wherein one of the first and second commands corresponding to the second target is generated according to a command set different from a standard volatile memory command set.

13. A storage node comprising:
a hybrid memory group comprising:
a non-volatile memory device; and
a volatile memory device coupled to the non-volatile memory device; and

a hybrid memory controller configured to perform data transfer to/from the volatile and non-volatile memory devices through a same channel, the hybrid memory controller comprising:
a processor; and
a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to perform:
identifying the volatile and non-volatile memory devices by detecting an associated serial presence detect (SPD) data stored in each of the volatile and non-volatile memory devices;
receiving a first central processing unit (CPU) request to write to/read from the hybrid memory group;
identifying the volatile memory device as a first target of the first CPU request by decoding and address mapping of the first CPU request;
queuing the first CPU request in a buffer;
receiving a second CPU request to write to/read from the hybrid memory group;
identifying the non-volatile memory device as a second target of the second CPU request by decoding and address mapping of the second CPU request;
queuing the second CPU request in the buffer;
determining an arbitration policy based on the SPD data associated with the volatile and non-volatile memory devices;
generating, based on the arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and, in response, generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets; and
transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

14. A method of controlling a hybrid memory group comprising a volatile memory device and a non-volatile memory device, the method comprising:
receiving, by a processor, a first central processing unit (CPU) request to write to/read from the hybrid memory group;
identifying, by the processor, the volatile memory device as a first target of the first CPU request by decoding and address mapping of the first CPU request;
queuing, by the processor, the first CPU request in a buffer;
receiving, by the processor, a second CPU request to write to/read from the hybrid memory group;
identifying, by the processor, the non-volatile memory device as a second target of the second CPU request by decoding and address mapping of the second CPU request;
queuing, by the processor, the second CPU request in the buffer;
generating, by the processor, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and, in response, generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets; and
transmitting, by the processor, the first and second commands to respective ones of the volatile and non-volatile memory devices.

15. The method of claim 14 , further comprising:
identifying, by the processor, the volatile and non-volatile memory devices by detecting an associated serial presence detect (SPD) data stored in each of the volatile and non-volatile memory devices;
identifying, by the processor, timing parameters of the volatile and non-volatile memory devices based on the associated SPD data; and
determining, by the processor, the arbitration policy based on the timing parameters.

16. The method of claim 14 , further comprising:
receiving, by the processor, a status feedback signal from the non-volatile memory device; and
determining, by the processor, the arbitration policy based on the status feedback signal.

17. The hybrid memory

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Niu Dimin
• Chang Mu-Tien
• Zheng Hongzhong
• Lim Sun Young
• Kim Indong

Classifications

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/068

  Hybrid storage device · CPC title