Memory system and read request management method thereof

Patent metadata

Field	Value
Publication number	US-2017123727-A1
Application number	US-201615215072-A
Country	US
Kind code	A1
Filing date	Jul 20, 2016
Priority date	Oct 30, 2015
Publication date	May 4, 2017
Grant date	—

Abstract

A memory system includes a plurality of memory devices and a memory controller configured to control the memory devices. The memory controller receives a read request having a variable size, generates at least one memory request having a fixed size in response to the read request, and transmits the at least one memory request to at least one of the memory devices.

First claim

What is claimed is:

1 . A memory system comprising:
a plurality of memory devices; and a memory controller configured to control the plurality of memory devices, wherein the memory controller is configured to receive a read request having a variable size, generate at least one memory request having a fixed size in response to the read request, and transmit the at least one memory request to at least one of the memory devices.

2 . The memory system of claim 1 , wherein the memory controller comprises a read queue configured to store the read request and a size of the read request.

3 . The memory system of claim 2 , wherein the memory controller further comprises a request size calculator configured to calculate the size of the read request using the fixed size.

4 . The memory system of claim 2 , wherein the read queue comprises a plurality of request queue units, and
the memory controller further comprises a scheduler configured to decide a read request to be processed among read requests stored in the request queue units.

5 . The memory system of claim 4 , wherein the memory controller further comprises a memory request generator configured to generate memory requests using a read request stored in a selected request queue unit from the scheduler and a corresponding size.

6 . The memory system of claim 1 , wherein the memory controller comprises a read queue having a plurality of request queue units configured to store the read request, and
wherein the request queue units are divided into a plurality of regions according to a size of the read request.

7 . The memory system of claim 6 , wherein the request queue units comprise:
a first size region having first request queue units; and a second size region having second request queue units, and a size of each of the second request queue units is greater than a size of each of the first request queue units.

8 . The memory system of claim 7 , wherein the memory controller further comprises an address splitter configured to receive the read request and split an address of the read request into a plurality of addresses responsive to size information of the read request, and
the split addresses are stored in a corresponding request queue unit among the second request queue units.

9 . The memory system of claim 6 , wherein the memory controller further comprises a request size calculator configured to receive the read request and calculate the size of the read request using the fixed size.

10 . The memory system of claim 6 , wherein the memory controller further comprises a scheduler configured to decide a read request to be processed among read requests stored in the request queue units, and
the scheduler is configured to decide a read request to be processed according to a score value accumulated in each of the request queue units.

11 . The memory system of claim 10 , wherein the scheduler is configured to select a corresponding request queue unit when the score value is greater than a predetermined value and select a request queue unit using a waiting time of each of the request queue units.

12 . The memory system of claim 10 , wherein the memory system is a key-value store, and
the scheduler is configured to decide priority according to a key and a value, and select a request queue unit using the decided priority and a size of a request queue unit.

13 . The memory system of claim 1 , wherein the memory controller comprises a memory request generator configured to
generate the at least one memory request, output a count value corresponding to a size of the read request, generate a memory address using a start address of the read request and a burst size of each of the memory devices, and determine whether a read request is the last memory request, based on the count value

14 . The memory system of claim 13 , wherein the memory request generator is configured to stop generating the memory address and generate a memory address for a new read request under a predetermined condition.

15 . A memory controller comprising:
a request size calculator configured to receive read requests and calculate a size of the read requests; a read queue comprising a plurality of request queue units configured to store the read requests; a scheduler configured to read information on the stored read requests from the read queue and select a processing sequence of the request queue units based on the read information; and a memory request generator configured to generate at least one memory request to a memory responsive to the processing sequence of the request queue units.

16 . The memory controller of claim 15 , wherein the read queue comprises first request queue units configured to store read requests of a first size, and second request queue units configured to store read requests of a second size greater than the first size.

17 . The memory controller of claim 16 , wherein the read request comprises a start address,
the memory controller further comprising an address splitter configured to split a single read request into first and second split read requests, and to store a start address of the first split read request in one of the first request queue units and a start address of the second split read request in one of the second request queue units.

18 . The memory controller of claim 15 , wherein the request size calculator is further configured to store the size of the read requests in the request queue units.

19 . A memory system, comprising:
a plurality of memory devices; and a memory controller configured to receive read requests, calculate sizes of the read requests, decide a processing sequence of the read requests using the calculated sizes and waiting times, and generate at least one memory request to at least one of the plurality of memory devices responsive to the read requests using the calculated sizes.

20 . The memory system of claim 19 , wherein the read requests have variable size.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong-Uk
• Kim Hanjoon
• LEE DuckJoo

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0611

  in relation to response time · CPC title