Architecture, system, method, and computer-accessible medium for expedited-compaction for scan power reduction

US10110226B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10110226-B2
Application numberUS-201213368963-A
CountryUS
Kind codeB2
Filing dateFeb 8, 2012
Priority dateFeb 24, 2011
Publication dateOct 23, 2018
Grant dateOct 23, 2018

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. Further, exemplary method, computer-accessible medium, and test configuration can be provided for testing at least on flip-flop that in which at least one scan-out channel having a plurality of regions, a plurality of compactors, and associating the plurality of compactors with the plurality of regions can be provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A test configuration, comprising: at least one scan-out channel having a plurality of regions, wherein the at least one scan-out channel includes at least one scan chain; and a plurality of identical compactors associated with the plurality of regions, wherein, during a first number of shift cycles, (i) all identical compactors are configured to be operated to finalize compaction of responses in a reference chain, and (ii) the at least one scan chain has all zero values; and wherein, during a second number of shift cycles, all identical compactors are configured to idle. 2. The test configuration of claim 1 , wherein each of the compactors is associated with a respective one of the regions. 3. The test configuration of claim 1 , wherein the first number of shift cycles is based on a ratio of a scan depth to a number of the identical compactors. 4. The test configuration of claim 1 , wherein the at least one scan-chain of a single region of the regions is coupled to an input of the respective one of the identical compactors associated with the single region. 5. The test configuration of claim 1 , wherein the at least one scan-chain includes the reference chain and at least one shadow chain. 6. The test configuration of claim 5 , further comprising a multiplexer which is coupled to each of the reference chains and the at least one shadow chain. 7. The test configuration of claim 6 , wherein the multiplexers coupled to the at least one shadow chain are configured to feed the zero values to the at least one shadow chain. 8. The test configuration of claim 1 , wherein the second number of shift cycles is based on a scan depth minus a ratio of the scan depth to a number of the identical compactor. 9. The test configuration of claim 1 , wherein each of the regions includes a group of consecutive scan slices, and wherein at least one of the scan slices includes one cell from each scan chain that is equal distance to the at least one scan-out channel. 10. The test configuration of claim 1 , wherein a ratio of a number of the identical compactors to a number of the regions is one. 11. The test configuration of claim 4 , wherein an output of the respective one of the identical compactors associated with a respective one of the regions is coupled to the reference chain of a downstream region of the regions. 12. A method for testing at least one flip-flop, comprising: providing at least one scan-out channel having a plurality of regions, wherein the at least one scan-out channel includes at least one scan chain; providing a plurality of identical compactors; associating the plurality of identical compactors with the plurality of regions; during a first number of shift cycles, (i) operating all identical compactors to finalize compaction of responses in a reference chain, and (ii) feeding all zero values to the at least one scan chain; and during a second number of shift cycles, idling all identical compactors. 13. The method of claim 12 , wherein the first number of shift cycles is based on a ratio of a scan depth to a number of the identical compactors. 14. The method of claim 12 , wherein the at least one scan-chain includes the reference chain and at least one shadow chain. 15. The method of claim 14 , further comprising coupling a multiplexer to each of the reference chains and the at least one shadow chain of a single region of the regions. 16. The method of claim 15 , further comprising feeding the zero values to the at least one shadow chain via the multiplexers coupled to each shadow chain. 17. The method of claim 12 , wherein the second number of shift cycles is based on a scan depth minus a ratio of the scan depth to a number of the identical compactors. 18. The method of claim 14 , wherein the at least one scan-chain of a single region of the regions is coupled to an input of the respective one of the identical compactors associated with the single region, and an output of the respective identical compactor is coupled to the reference chain of a downstream region of the regions. 19. A non-transitory computer readable medium including instructions thereon that are accessible by a hardware processing arrangement, wherein, when the processing arrangement executes the instructions, the processing arrangement is configured to: provide at least one scan-out channel having a plurality of regions, wherein the at least one scan-out channel includes at least one scan chain; provide a plurality of identical compactors; associate the plurality of identical compactors with the plurality of regions; during a first number of shift cycles, (i) operate all identical compactors to finalize compaction of responses in a reference chain and (ii) feed all zero values to the at least one scan chain; and during a second number of shift cycles, idle all identical compactors. 20. The non-transitory computer readable medium of claim 19 , wherein the at least one scan-out channel includes the reference chain and at least one shadow chain, and the processing arrangement is further configured to provide a multiplexer for each of the at least one scan-chain. 21. The non-transitory computer readable medium of claim 20 , wherein the multiplexers are configured to feed the zero values to the at least one shadow chain via the multiplexers coupled to each shadow chain. 22. The non-transitory computer readable medium of claim 19 , wherein the first number of shift cycles is based on a ratio of a scan depth to a number of the identical compactors. 23. The non-transitory computer readable medium of claim 20 , wherein the at least one scan-chain of a single region of the regions is input into to the respective one of the identical compactors associated with the single region, and an output of the respective identical compactor is coupled to the reference chain of a downstream region of the regions. 24. The non-transitory computer readable medium of claim 19 , wherein the second number of shift cycles is based on a scan depth minus a ratio of the scan depth to a number of the identical compactors. 25. A test configuration comprising: at least one scan-out channel having a plurality of regions, each of the regions including at least one scan cell, wherein the at least one scan-out channel includes at least one scan chain, and wherein the at least one scan-chain includes a reference chain and at least one shadow chain; and a plurality of compactors associated with the plurality of regions, wherein the compactors comprise a first compactor and a second compactor, the regions comprise a first region and a second region, the first compactor is positioned between the first region and the second region, the second compactor is positioned after the second region, during a first number of shift cycles, (i) all compactors are configured to be operated to finalize compaction of responses in a reference chain, and (ii) the at least one scan chain has all zero values; and during a second number of shift cycles, all compactors are configured to idle. 26. The test configuration of claim 25 , wherein the first number of shift cycles is based on a ratio of a scan depth to a number of the compactors. 27. The test configuration of claim 25 , further comprising a multiplexer which is coupled to the reference chain and at least one shadow chain. 28. The test configuration of

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  • Arrangements for reducing power consumption · CPC title

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What does patent US10110226B2 cover?
Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. Further, exemplary method, computer-accessible medium, and test configuration can be p…
Who is the assignee on this patent?
Sinanoglu Ozgur, Univ New York
What technology area does this patent fall under?
Primary CPC classification H03K19/0008. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 23 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).