Semiconductor device

Patent metadata

Field	Value
Publication number	US-10109982-B2
Application number	US-201715426256-A
Country	US
Kind code	B2
Filing date	Feb 7, 2017
Priority date	Aug 12, 2014
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A semiconductor device includes: a semiconductor layered structure including an active layer, a first region including a part of the active layer and extending in a layered direction, a second region including at least a part of an end portion of the active layer and extending in the layered direction, disordering of the second region being higher than the first region, and a third region including a portion of the active layer between the first region and the second region and extending in the layered direction, disordering of the third region being higher than the first region and lower than the second region; and an electrode configured to inject an electric current to the active layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layered structure including
an active layer,
a first region including a part of the active layer and extending in a layered direction,
a second region including at least a part of an end portion of the active layer and extending in the layered direction, disordering of the second region being higher than the first region, and
a third region including a portion of the active layer between the first region and the second region and extending in the layered direction, disordering of the third region being higher than the first region and lower than the second region; and

an electrode configured to inject an electric current to the active layer, wherein
the semiconductor layered structure includes an upper impurity layer doped with an impurity in an outermost region in the layered direction, and a lower impurity layer formed between the active layer and the upper impurity layer, the lower impurity layer having lower impurity concentration than the upper impurity layer,
at least the outermost region of the first region and the third region has the upper impurity layer,
the lower impurity layer is exposed from an outermost surface of the semiconductor layered structure in at least a part of the second region, and
the lower impurity layer is exposed from the outermost surface of the semiconductor layered structure in the third region near a boundary of the third region and the first region.

2. The semiconductor device according to claim 1 , wherein a failure-mode-generating region is positioned near the second region in the third region, and a failure due to a failure mode originating from the failure-mode-generating region is suppressed.

3. The semiconductor device according to claim 1 , wherein
the upper impurity layer is an upper first impurity layer doped with a first impurity accelerating disordering, and
the lower impurity layer is a lower first impurity layer whose concentration of the first impurity is lower than the upper first impurity layer.

4. The semiconductor device according to claim 1 , wherein a width, in a predetermined direction, of the upper impurity layer in the third region is 3 μm or more.

5. The semiconductor device according to claim 1 , wherein a width, in a predetermined direction, of a region in which the lower impurity layer is exposed in the third region is 2 μm or more.

6. The semiconductor device according to claim 1 , wherein the electrode contacts the upper impurity layer of the first region and is isolated from the upper impurity layer of the third region.

7. The semiconductor device according to claim 3 , wherein
the semiconductor layered structure includes the first impurity between the outermost surface of the semiconductor layered structure and the active layer, and
a relationship of C 12 ≥C 13 ≥C 11 is satisfied where C 11 is a contained amount of the first impurity in the first region, C 12 is a contained amount of the first impurity in the second region, and C 13 is a contained amount of the first impurity in the third region.

8. The semiconductor device according to claim 3 , wherein
the semiconductor layered structure includes a second impurity between an outermost surface of the semiconductor layered structure and the active layer, the second impurity suppressing the disordering, and
a relationship of C 21 ≥C 23 ≥C 22 is satisfied where C 21 is a contained amount of the second impurity in the first region, C 22 is a contained amount of the second impurity in the second region, and C 23 is a contained amount of the second impurity in the third region.

9. The semiconductor device according to claim 1 , wherein a length of the active layer of the third region in at least a predetermined direction among directions to the first region in parallel with the active layer is 5 μm or more.

10. The semiconductor device according to claim 1 , wherein the third region includes an inert atom more than the second region.

11. The semiconductor device according to claim 1 , wherein
the semiconductor device is an edge-emission-type semiconductor laser device, and
a predetermined direction is a direction in which light is guided in the semiconductor laser device.

12. The semiconductor device according to claim 11 , wherein a length of the active layer of the third region in the predetermined direction is 5 μm or more in an entire region in which the light is guided.

13. The semiconductor device according to claim 1 , wherein a length of the active layer of the third region is 5 μm or more in any direction from the third region toward the first region in parallel with the active layer.

14. The semiconductor device according to claim 1 , wherein the disordering of the third region changes from a value identical to the disordering of the second region near a boundary of the third region and the second region to a value identical to the disordering of the first region near a boundary of the third region and the first region.

15. The semiconductor device according to claim 14 , wherein the disordering of the third region changes in an approximate tapered shape in any direction from a boundary of the third region and the second region to a boundary of the third region and the first region in parallel with the active layer.

16. The semiconductor device according to claim 14 , wherein the disordering of the third region changes in an approximate stepped shape in any direction from a boundary of the third region and the second region to a boundary of the third region and the first region in parallel with the active layer.

17. The semiconductor device according to claim 14 , wherein the disordering of the third region decreases rapidly near the first region in any direction from a boundary of the third region and the second region to a boundary of the third region and the first region in parallel with the active layer.

18. The semiconductor device according to claim 14 , wherein the disordering of the third region repeatedly increases and decreases in any direction from a boundary of the third region and the second region to a boundary of the third region and the first region in parallel with the active layer.

Assignees

• Furukawa Electric Co Ltd

Inventors

• Taniguchi Hidehiro

Classifications

• H01S5/04254

  characterised by the shape · CPC title

• H01S5/4031

  Edge-emitting structures · CPC title

• H01S5/3209

  disordered active layer · CPC title

• H01S5/22

  having a ridge or stripe structure · CPC title

• H01S5/162 Primary

  with window regions made by diffusion or disordening of the active layer · CPC title