Semiconductor device with an isolation structure coupled to a cover of the semiconductor device

Patent metadata

Field	Value
Publication number	US-10109594-B2
Application number	US-201615136326-A
Country	US
Kind code	B2
Filing date	Apr 22, 2016
Priority date	Aug 5, 2014
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first electrical circuit on the substrate;
a second electrical circuit on the substrate;
a cover on the substrate, the cover comprising first and second side walls between which a primary wall extends; and
an isolation structure comprising a first leg in contact with the first side wall and a first cross member in contact with the primary wall and connected to the first leg, wherein the first leg is electrically connected to a ground potential node of at least one of the first electrical circuit and the second electrical circuit, and wherein the isolation structure is configured to reduce electromagnetic coupling between the first electrical circuit and the second electrical circuit during an operation of the semiconductor device.

2. The semiconductor device as recited in claim 1 , further comprising a capacitor coupling the first leg to the ground potential node.

3. The semiconductor device as recited in claim 1 , wherein the isolation structure further comprises a second leg in contact with the second side wall and connected to the first cross member.

4. The semiconductor device as recited in claim 3 , wherein the first leg comprises a first electrical connector mounted on and projecting outward from the substrate; wherein the second leg comprises a second electrical connector mounted on and projecting outward from the substrate; and wherein the first cross member has a first aperture into which the first electrical connector extends and a second aperture into which the second electrical connector extends.

5. The semiconductor device as recited in claim 1 , wherein the isolation structure further comprises a second cross member in contact with the primary wall and coupled to the first cross member.

6. The semiconductor device as recited in claim 1 , wherein the isolation structure further comprises an additional leg in contact with one of the first side wall and the second side wall; and a second cross member in contact with the primary wall and connected to the additional leg.

7. The semiconductor device as recited in claim 6 , wherein the first cross member is connected in common with the second cross member.

8. The semiconductor device as recited in claim 1 , wherein the first leg and a portion of the first cross member comprises a first electrical connector mounted on and projecting outward from the substrate, wherein the first electrical connector extends adjacent to the first side wall and to the primary wall, and a portion of the first cross member comprises a second electrical connector mounted on and projecting outward from the substrate, wherein the second electrical connector extends adjacent to the second side wall and to the primary wall.

9. The semiconductor device as recited in claim 8 , wherein the first electrical connector is connected to the second electrical connector at a point adjacent to the primary wall.

10. A semiconductor device comprising:
a substrate having a surface;
an electronic device on the substrate and comprising a first electrical component and a second electrical component;
a cover on the substrate, wherein the cover extends over at least a portion of the first and second electrical components and comprises a primary wall extending from a first side wall and to a second side wall;
a first electrical connector on the first side wall of the cover;
a second electrical connector on the second side wall of the cover; and
an isolation structure comprising a first cross member on the primary wall and extending in between the first electrical component and the second electrical component, the first cross member connected to both the first electrical connector and the second electrical connector, wherein the isolation structure is configured to reduce electromagnetic coupling between the first electrical component and the second electrical component during an operation of the electronic device.

11. The semiconductor device as recited in claim 10 , wherein the first cross member has a first aperture into which the first electrical connector extends and a second aperture into which the second electrical connector extends.

12. The semiconductor device as recited in claim 10 , wherein each of the first and second electrical connectors has a section configured to connect to a printed circuit board on which the semiconductor device is mounted.

13. The semiconductor device as recited in claim 10 , wherein the first cross member is attached to the first electrical connector and the second electrical connector by one of solder and electrically conductive epoxy.

Assignees

• Freescale Semiconductor Inc
• Nxp Usa Inc

Inventors

• Viswanathan Lakshminarayan
• Watts Michael E
• Abdo David F

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title