Semiconductor device

Patent metadata

Field	Value
Publication number	US-10109565-B2
Application number	US-201615380183-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	Dec 18, 2015
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Miniaturization of a semiconductor device is attained. An SOP 1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP 1 , the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor chip having a surface over which a plurality of first pads are formed;
a second semiconductor chip having a surface over which a plurality of second pads are formed;
a first chip mounting part over which the first semiconductor chip is mounted;
a second chip mounting part over which the second semiconductor chip is mounted;
a plurality of leads arranged around the first semiconductor chip and the second semiconductor chip;
a plurality of first wires electrically coupling the first pads of the first semiconductor chip with a plurality of first leads among the leads, respectively;
a plurality of second wires electrically coupling the second pads of the second semiconductor chip with a plurality of second leads among the leads, respectively; and
a sealing body having a first surface and a second surface facing the first surface and sealing the first semiconductor chip, the second semiconductor chip, the first chip mounting part, the second chip mounting part, the first wires, and the second wires,
wherein the first semiconductor chip includes, among the first pads, the first pads to which a first power supply is supplied,
wherein the second semiconductor chip includes, among the second pads, the second pads to which a second power supply whose voltage is greater than that of the first power supply is supplied,
wherein, in plan view, the first semiconductor chip and the first chip mounting part are immediately adjacent to, but do not overlap, the second semiconductor chip and the second chip mounting part, and
wherein, in cross sectional view along a first direction between the first surface and the second surface of the sealing body, with respect to a second direction in which the first surface extends, the first semiconductor chip and the first chip mounting part are immediately adjacent to, but do not overlap, the second semiconductor chip and the second chip mounting part.

2. The semiconductor device according to claim 1 ,
wherein the number of the second pads of the second semiconductor chip is greater than the number of the first pads of the first semiconductor chip, and
wherein the second chip mounting part is arranged below the first chip mounting part.

3. The semiconductor device according to claim 1 ,
wherein an area of the surface of the second semiconductor chip is larger than an area of the surface of the first semiconductor chip, and
wherein the second chip mounting part is arranged below the first chip mounting part.

4. The semiconductor device according to claim 1 ,
wherein the sealing body has four sides in plan view,
wherein, in plan view, the leads are arranged along one pair of opposing sides among the four sides of the sealing body, and
wherein the leads electrically coupled to one of the first semiconductor chip, the second semiconductor chip, the first chip mounting part, and the second chip mounting part are not arranged, in plan view, along the other pair of opposing sides among the four sides of the sealing body.

5. The semiconductor device according to claim 1 ,
wherein the first semiconductor chip includes a transmission part for transmitting a signal to the outside and a reception part for receiving a signal from the outside, and
wherein the transmission part includes: a transmission circuit; a first coil electrically coupled with the transmission circuit; and a second coil which is arranged over the first coil through an insulating layer, and is electrically coupled with some pads among the first pads.

6. The semiconductor device according to claim 1 , wherein the first chip mounting part and the second chip mounting part are arranged through part of the sealing body.

7. The semiconductor device according to claim 1 , wherein some pads among the first pads of the firs semiconductor chip are electrically coupled to some pads among the second pads of the second semiconductor chip, respectively, through a plurality of third wires.

8. A semiconductor device, comprising:
a first semiconductor chip having a surface over which a plurality of first pads are formed;
a second semiconductor chip having a surface over which a plurality of second pads are formed;
a first chip mounting part over which the first semiconductor chip is mounted;
a second chip mounting part over which the second semiconductor chip is mounted;
a plurality of leads arranged around the first semiconductor chip and the second semiconductor chip;
a plurality of first wires electrically coupling the first pads of the first semiconductor chip with a plurality of first leads among the leads, respectively;
a plurality of second wires electrically coupling the second pads of the second semiconductor chip with a plurality of second leads among the leads, respectively; and
a sealing body having a first surface and a second surface facing the first surface and sealing the first semiconductor chip, the second semiconductor chip, the first chip mounting part, the second chip mounting part, the first wires, and the second wires,
wherein the first semiconductor chip includes, among the first pads, the first pads to which a first power supply is supplied,
wherein the second semiconductor chip includes, among the second pads, the second pads to which a second power supply whose voltage is greater than that of the first power supply is supplied,
wherein in cross sectional view along a first direction between the first surface and the second surface of the sealing body, with respect to a second direction in which the first surface extends, either the first semiconductor chip and the first chip mounting part or the second semiconductor chip and the second chip mounting part are arranged above an upper surface of the leads, and the other of the first semiconductor chip and the first chip mounting part or the second semiconductor chip and the second chip mounting part are arranged below the upper surface of the leads,
wherein, in plan view, the first semiconductor chip and the first chip mounting part are immediately adjacent to, but do not overlap, the second semiconductor chip and the second chip mounting part, and
wherein a distance between the chip mounting parts in plan view is shorter than any of a distance between the first chip mounting part and the second chip mounting part in cross sectional view, a distance between the second semiconductor chip and the first chip mounting part in cross sectional view when the first semiconductor chip and the first chip mounting part are arranged above the upper surface of the leads, and a distance between the first semiconductor chip and the second chip mounting part in cross sectional view when the second semiconductor chip and the second chip mounting part are arranged above the upper surface of the leads.

9. The semiconductor device according to claim 8 ,
wherein the number of the second pads of the second semiconductor chip is greater than the number of the first pads of the first semiconductor chip, and
wherein the second chip mounting part is arranged below the first chip mounting part.

10. The semiconductor device according to claim 8 ,
wherein an area of the surface of the second semiconductor chip is larger than an area of the surface of the first semiconductor chip, and
wherein the second chip mounting part is arranged below the first chip mounting part.

11. The semiconductor device according to claim 8 ,
wherein the sealing body has four sides in plan view,
wherein, in plan view, the leads are arranged along one pair of opposing sides among the four sides of the sealing body, and
wherein, in plan view, the leads electrically coupled to one o

Assignees

• Renesas Electronics Corp

Inventors

• Takada Keita
• Danno Tadatoshi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/751

  of bond wires · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title