Vertical FET with selective atomic layer deposition gate

Patent metadata

Field	Value
Publication number	US-10109491-B2
Application number	US-201615342585-A
Country	US
Kind code	B2
Filing date	Nov 3, 2016
Priority date	Jan 27, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Vertical channel field effect transistors include a bottom source/drain layer. One or more vertical channels are formed on the bottom source/drain layer. A horizontal seed layer is formed around the one or more vertical channels. A metal gate is formed directly on the seed layer. A top source/drain is formed layer above the one or more vertical channels and the metal gate.

First claim

The invention claimed is:

1. A field effect transistor, comprising:
a bottom source/drain layer;
one or more vertical channels on the bottom source/drain layer;
a horizontal seed layer around the one or more vertical channels;
a metal gate directly on the seed layer; and
a top source/drain layer above the one or more vertical channels and the metal gate; a work function metal layer formed directly on sidewalls of the one or more vertical channels.

2. The field effect transistor of claim 1 , wherein the seed layer is formed from a different material from the metal gate.

3. The field effect transistor of claim 2 , wherein the seed layer is silicon and where the metal gate is tungsten, nucleated on the seed layer.

4. The field effect transistor of claim 1 , further comprising a bottom spacer directly on the bottom source/drain region, under the seed layer.

5. The field effect transistor of claim 4 , further comprising a work function metal layer directly on the bottom spacer, directly under the seed layer.

6. The field effect transistor of claim 5 , wherein the work function metal is formed along sidewalls of the metal gate.

7. The field effect transistor of claim 5 , wherein the work function metal does not extend over the metal gate.

8. The field effect transistor of claim 5 , wherein the work function metal layer is formed directly on sidewalls of the one or more vertical channels.

9. The field effect transistor of claim 1 , further comprising a top spacer directly on the metal gate.

10. The field effect transistor of claim 9 , wherein the top source/drain layer is directly on the top spacer.

11. The field effect transistor of claim 9 , wherein a top surface of the top spacer is level with a top surface of the one or more vertical channels.

12. The field effect transistor of claim 1 , wherein the seed layer has a thickness between about 1 nm and about 2 nm.

13. A field effect transistor, comprising:
a bottom source/drain layer;
a bottom spacer directly on the bottom source/drain layer;
one or more vertical channels directly on the bottom source/drain layer;
a work function metal layer directly on the bottom spacer;
a horizontal seed layer around the one or more vertical channels, directly on the work function metal layer;
a metal gate directly on the seed layer;
a top spacer directly on the metal gate; and
a top source/drain layer directly on the top spacer and the one or more vertical channels.

14. The field effect transistor of claim 13 , wherein the seed layer is formed from a different material from the metal gate.

15. The field effect transistor of claim 14 , wherein the seed layer is silicon and where the metal gate is tungsten, nucleated on the seed layer.

16. The field effect transistor of claim 13 , wherein the work function metal is formed along sidewalls of the metal gate.

17. The field effect transistor of claim 13 , wherein a top surface of the top spacer is level with a top surface of the one or more vertical channels.

18. A field effect transistor, comprising:
a bottom source/drain layer;
a bottom spacer directly on the bottom source/drain layer;
one or more vertical channels directly on the bottom source/drain layer;
a work function metal layer directly on the bottom spacer;
a horizontal seed layer around the one or more vertical channels, directly on the work function metal layer;
a metal gate directly on the seed layer and formed from a different material from the seed layer, wherein the work function metal is formed along sidewalls of the metal gate;
atop spacer directly on the metal gate, wherein a top surface of the top spacer is level with a top surface of the one or more vertical channels; and
a top source/drain layer directly on the top spacer and the one or more vertical channels; a work function metal layer formed directly on sidewalls of the one or more vertical channels.

19. The field effect transistor of claim 18 , wherein the seed layer is silicon and where the metal gate is tungsten, nucleated on the seed layer.

Assignees

• IBM
• Intenational Business Machines Corp

Inventors

• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6514

  by exposure to a plasma · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2923

  being conductive materials, e.g. metallic silicides · CPC title

• H10P14/432

  using selective deposition · CPC title