Method for producing a superjunction device

Patent metadata

Field	Value
Publication number	US-10109489-B2
Application number	US-201715648987-A
Country	US
Kind code	B2
Filing date	Jul 13, 2017
Priority date	Jul 14, 2016
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Disclosed is a method that includes forming a plurality of semiconductor arrangements one above the other. In this method, forming each of the plurality of semiconductor arrangements includes: forming a semiconductor layer; forming a plurality of trenches in a first surface of the semiconductor layer; and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer.

First claim

What is claimed is:

1. A method, comprising:
forming at least one semiconductor arrangement, wherein forming the at least one semiconductor arrangement includes forming a semiconductor layer;
forming a plurality of trenches in a first surface of the semiconductor layer; and
implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches of the semiconductor layer,
wherein the at least one semiconductor arrangement comprises at least one pair of semiconductor arrangements with a bottom semiconductor arrangement and a top semiconductor arrangement adjoining the bottom semiconductor arrangement,
wherein forming the semiconductor layer of the top semiconductor arrangement comprises forming a top semiconductor layer in the plurality of trenches and on top of mesa regions between the plurality of trenches of the semiconductor layer of the bottom semiconductor arrangement, and forming a plurality of trenches in the top semiconductor layer,
wherein the plurality of trenches of the top semiconductor arrangement are substantially aligned with the plurality of trenches of the bottom semiconductor arrangement.

2. The method of claim 1 , wherein forming the semiconductor layer comprises epitaxially growing the semiconductor layer.

3. The method of claim 2 , wherein epitaxially growing the semiconductor layer comprises epitaxially growing the semiconductor layer until the first surface of the semiconductor layer is substantially planar.

4. The method of claim 1 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of the first type into the first sidewall; and
implanting dopant atoms of the second type into the second sidewall.

5. The method of claim 1 , wherein implanting the dopant atoms comprises implanting dopant atoms of both the first type and the second type into at least one of the first sidewall and the second sidewall.

6. The method of claim 5 , wherein implanting dopant atoms of both the first type and the second type into at least one of the first sidewall and the second sidewall comprises implanting molecules that include dopant atoms of both the first type and the second type into at least one of the first sidewall and the second sidewall.

7. The method of claim 5 , further comprising:
annealing the semiconductor layer so that dopant atoms of the first type and the second type diffuse in the semiconductor layer.

8. The method of claim 7 , further comprising:
generating interstitials in the semiconductor layer.

9. The method of claim 1 , wherein forming the plurality of trenches comprises a wet etching process.

10. The method of claim 1 , wherein an aspect ratio of each of the plurality of trenches is between 10:1 and 1:1, or between 6:1 and 1:1.

11. The method of claim 1 , wherein a semiconductor material of the semiconductor layer is silicon, and wherein the first surface lies in a {110} plane of a crystal lattice of the semiconductor layer.

12. The method of claim 11 , wherein forming the plurality of trenches comprises forming the plurality of trenches such that both the first sidewall and the second sidewall lie in a {111} plane of the crystal lattice.

13. The method of claim 1 , further comprising:
annealing the at least one pair of semiconductor arrangements to diffuse the dopant atoms.

14. The method of claim 1 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of the first type at a first implantation dose into at least one of the first sidewall and the second sidewall; and
implanting dopant atoms of the second type at a second implantation dose into at least one of the first sidewall and the second sidewall,
wherein a magnitude of a difference between the first implantation dose and the second implantation dose is less than 20% of each of the first implantation dose and the second implantation dose.

15. The method of claim 1 , wherein each of the plurality of trenches has a width in a first lateral direction and a length in a second lateral direction perpendicular to the first lateral direction, and wherein the length is at least 10 times, at least 100 times, at least 1000 times, or at least 10000 times the width.

16. The method of claim 1 , wherein implanting dopant atoms of the at least one of the first type and the second type into the least one of the first sidewall and the second sidewall of each of the plurality of trenches of the semiconductor layer comprises at least two implantation processes that use different implantation angles.

17. The method of claim 1 , wherein implanting the dopant atoms comprises implanting dopant atoms of one of the first and second type into deeper sidewall sections than dopant atoms of the other one of the first and second type.

18. A method of forming a semiconductor device comprising:
forming a first semiconductor layer;
forming a first plurality of trenches in the first semiconductor layer;
implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the first plurality of trenches of the first semiconductor layer;
forming a second semiconductor layer in the first plurality of trenches and on mesa regions between the first plurality of the trenches of the first semiconductor layer;
forming a second plurality of trenches in the second semiconductor layer;
implanting the dopant atoms of the at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the second plurality of trenches of the second semiconductor layer; and
annealing the first and second semiconductor layers to diffuse the implanted dopant atoms to form alternating vertical regions of the first type and the second type.

19. The method of claim 18 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of the first type into the first sidewalls of the first and second plurality of trenches; and
implanting dopant atoms of the second type into the second sidewalls of the first and second plurality of trenches.

20. The method of claim 18 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of the first type into the first sidewalls of the first and second plurality of trenches; and
implanting dopant atoms of the first type into the second sidewalls of the first and second plurality of trenches.

21. The method of claim 18 , wherein implanting the dopant atoms comprises:
implanting dopant atoms of the first type and the second type into the first and second sidewalls of the first and second plurality of trenches.

22. The method of claim 18 , further comprising:
forming a third semiconductor layer in the second plurality of trenches and on mesa regions between the second plurality of the trenches of the second semiconductor layer;
forming a third plurality of trenches in the third semiconductor layer;
implanting the dopant atoms of the at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the third plurality of trenches of the third semiconductor layer; and
annealing the first, second and third semiconductor layers to diffuse the implanted dopant atoms to form alternating vertical regions of the first type and the second type.

23. The method of claim 22 , further comprising:
forming a fourth semiconductor layer in the third pl

Assignees

• Infineon Technologies Austria Ag

Inventors

• Mauder Anton
• Weber Hans
• Hirler Franz
• Laven Johannes Georg
• Schulze Hans-Joachim
• Schustereder Werner
• Treiber Maximilian
• Tutuc Daniel
• Voerckel Andreas

Classifications

• H10P30/222 Primary

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P95/906

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H01L29/7813

  Electricity · mapped topic