Conductive hard mask for memory device formation

Patent metadata

Field	Value
Publication number	US-10103326-B2
Application number	US-201715855657-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Mar 11, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

First claim

What is claimed is:

1. A memory cell apparatus, comprising:
a first memory element that comprises a variable resistance material;
a first electrode coupled with the first memory element;
at least a portion of a conductive hard mask coupled with the first electrode;
a conductive line coupled with the first electrode via the conductive hard mask, wherein the conductive hard mask comprises a portion having a first thickness; and
a second memory element that comprises the variable resistance material; and
a second electrode coupled with the second memory element, wherein the conductive line is coupled with the second electrode via the conductive hard mask, and wherein the conductive hard mask comprises a portion having a second thickness different from the first thickness.

2. The memory cell apparatus of claim 1 , further comprising:
a sealant coupled with the first memory element, the first electrode, and at least a portion of the conductive hard mask, wherein the sealant comprises a different material than the conductive hard mask.

3. The memory cell apparatus of claim 1 , further comprising:
at least one interconnect.

4. A memory cell apparatus, comprising:
a first memory element that comprises a variable resistance material;
a first electrode coupled with the first memory element;
at least a portion of a conductive hard mask coupled with the first electrode;
a conductive line coupled with the first electrode via the conductive hard mask, wherein the conductive hard mask comprises a portion having a first thickness;
a second memory element that comprises the variable resistance material; and
a second electrode coupled with the second memory element, wherein the conductive line is coupled directly to the second electrode.

5. The memory cell apparatus of claim 1 , wherein the conductive hard mask and the conductive line comprise a same material.

6. The memory cell apparatus of claim 1 , wherein the conductive hard mask comprises at least one of tungsten, aluminum, titanium, titanium nitride, silicon, or any combination thereof.

7. A memory cell apparatus, comprising:
a first memory element that comprises a variable resistance material;
a first electrode coupled with the first memory element; and
at least a portion of a conductive hard mask coupled with the first electrode, wherein the conductive hard mask comprises a set of sublayers, wherein each sublayer of the set comprises a different conductive material.

8. The memory cell apparatus of claim 1 , wherein the variable resistance material comprises a chalcogenide material.

9. The memory cell apparatus of claim 4 , further comprising:
a sealant coupled with the first memory element, the first electrode, and at least a portion of the conductive hard mask, wherein the sealant comprises a different material than the conductive hard mask.

10. The memory cell apparatus of claim 4 , further comprising:
at least one interconnect.

11. The memory cell apparatus of claim 4 , wherein the conductive hard mask and the conductive line comprise a same material.

12. The memory cell apparatus of claim 4 , wherein the conductive hard mask comprises at least one of tungsten, aluminum, titanium, titanium nitride, silicon, or any combination thereof.

13. The memory cell apparatus of claim 4 , wherein the variable resistance material comprises a chalcogenide material.

14. The memory cell apparatus of claim 4 , wherein the conductive hard mask comprises a set of sublayers, wherein each sublayer of the set comprises a different conductive material.

15. The memory cell apparatus of claim 7 , further comprising:
a sealant coupled with the first memory element, the first electrode, and at least a portion of the conductive hard mask, wherein the sealant comprises a different material than the conductive hard mask.

16. The memory cell apparatus of claim 7 , further comprising:
at least one interconnect.

17. The memory cell apparatus of claim 7 , wherein the conductive hard mask comprises at least one of tungsten, aluminum, titanium, titanium nitride, silicon, or any combination thereof.

18. The memory cell apparatus of claim 7 , wherein the variable resistance material comprises a chalcogenide material.

19. The memory cell apparatus of claim 7 , further comprising:
a conductive line coupled with the first electrode via the conductive hard mask, wherein the conductive hard mask comprises a portion having a first thickness.

20. The memory cell apparatus of claim 19 , wherein the conductive hard mask and the conductive line comprise a same material.

Assignees

• Micron Technology Inc

Inventors

• Bernhardt Michael
• Lindenberg Tony
• Zhang Wenzhe
• Capson Douglas

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• H01L45/126

  Electricity · mapped topic

• H01L45/142

  Electricity · mapped topic