Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10103236-B2
Application number	US-201715591736-A
Country	US
Kind code	B2
Filing date	May 10, 2017
Priority date	Dec 10, 2014
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A method for manufacturing a semiconductor device includes forming a conductive pattern on a substrate, forming a filling insulation layer covering the conductive pattern, forming a contact hole in the filling insulation layer and adjacent to the conductive pattern, forming an opening in the conductive pattern by removing a portion of the conductive pattern adjacent to the contact hole such that the opening is connected to the contact hole, and forming a contact plug filling the contact hole and the opening. A width of the opening is greater than a width of the contact hole.

First claim

What is claimed is:

1. A semiconductor device comprising:
a stack structure on a substrate, the stack structure including a plurality of conductive patterns stacked on the substrate; and
a plurality of contact plugs connected to the plurality of conductive patterns respectively,
wherein at least one of the plurality of contact plugs includes a contact plate in a corresponding one of the plurality of conductive patterns and a contact body on the contact plate, and
wherein the contact plate has a circular shape in a plan view.

2. The semiconductor device of claim 1 , wherein each of the plurality of conductive patterns includes an end portion, the end portions of the plurality of conductive patterns defining a stepwise structure, and
wherein the contact plate is in the end portion of the corresponding one of the plurality of conductive patterns.

3. The semiconductor device of claim 2 , further comprising an interlayer insulating layer covering the stepwise structure,
wherein the contact body penetrates the interlayer insulating layer.

4. The semiconductor device of claim 2 , wherein the stack structure further including a plurality of insulating patterns, the plurality of insulating patterns and the plurality of conductive patterns being alternatively stacked on the substrate, and
wherein the contact body penetrates a corresponding one of the plurality of insulating patterns.

5. The semiconductor device of claim 1 , wherein the contact plate penetrates the corresponding one of the plurality of conductive patterns.

6. The semiconductor device of claim 1 , wherein a width of the contact plate is greater than a width of the contact body.

7. The semiconductor device of claim 1 , wherein the plurality of contact plugs have different heights from each other.

8. The semiconductor device of claim 1 , further comprising a plurality of vertical channel structures on the substrate,
wherein each of the plurality of vertical channel structures penetrates the plurality of conductive patterns.

9. The semiconductor device of claim 1 , wherein the corresponding one of the plurality of conductive patterns is a lowest one of the plurality of conductive patterns.

10. A semiconductor device comprising:
a stack structure on a substrate, the stack structure including a plurality of conductive patterns stacked on the substrate; and
a plurality of contact plugs connected to the plurality of conductive patterns respectively,
wherein at least one of the plurality of contact plugs includes a contact plate in a corresponding one of the plurality of conductive patterns and a contact body on the contact plate, and
wherein a level of a bottom surface of the contact plate is substantially the same with a level of a bottom surface of the corresponding one of the plurality of conductive patterns.

11. The semiconductor device of claim 10 , wherein the bottom surface of the contact plate is substantially parallel to a top surface of the substrate.

12. The semiconductor device of claim 10 , wherein a level of a top surface of the contact plate is substantially the same with a level of a top surface of the corresponding one of the plurality of conductive patterns.

13. The semiconductor device of claim 10 , wherein each of the plurality of conductive patterns includes an end portion, the end portions of the plurality of conductive patterns defining a stepwise structure, and
wherein the contact plate is in the end portion of the corresponding one of the plurality of conductive patterns.

14. The semiconductor device of claim 13 , wherein the stack structure further including a plurality of insulating patterns, the plurality of insulating patterns and the plurality of conductive patterns being alternatively stacked on the substrate, and
wherein the contact body penetrates a corresponding one of the plurality of insulating patterns.

15. A method for manufacturing a semiconductor device, the method comprising:
forming a stack structure including a plurality of conductive patterns stacked on a substrate, the plurality of conductive patterns defining a stepwise structure;
forming a interlayer insulating layer covering the stepwise structure; and
forming a plurality of contact plugs connected to the plurality of conductive patterns respectively,
wherein forming at least one of the plurality of contact plugs comprises:
forming a contact hole in the interlayer insulating layer toward a corresponding one of the plurality of conductive patterns;
forming an opening in the corresponding one of the plurality of conductive patterns; and
forming the at least one of the plurality of contact plugs in the contact hole and the opening,
wherein at least one of the plurality of contact plugs includes a contact plate in a corresponding one of the plurality of conductive patterns, and
wherein the contact plate has a circular shape in a plan view.

16. The method of claim 15 , wherein each of the plurality of conductive patterns has an end portion, the end portions of the plurality of conductive patterns defining a stepwise structure, and
wherein the opening is formed in the end portion of the corresponding one of the plurality of conductive patterns.

17. The method of claim 15 , wherein the opening is formed to extend from a top surface of the corresponding one of the plurality of conductive patterns to a bottom surface of the corresponding one of the plurality of conductive patterns.

18. The method of claim 15 , wherein forming the opening is performed using a wet etching process.

19. The method of claim 18 , wherein an etch rate of the corresponding one of the plurality of conductive patterns is higher than an etch rate of interlayer insulating layer during the wet etching process.

20. The method of claim 18 , wherein forming the contact hole includes leaving a residue of the interlayer insulating layer between the corresponding one of the plurality of conductive patterns and a bottom of the contact hole, and
wherein forming the opening includes removing the residue using the wet etching process.

Assignees

• Lim Tae Wan
• Kang Hojong
• Park Joowon
• Samsung Electronics Co Ltd

Inventors

• Lim Tae-Wan
• Kang Hojong
• Park Joowon

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title