Dual-sided silicon integrated passive devices

Patent metadata

Field	Value
Publication number	US-10103138-B2
Application number	US-201715658670-A
Country	US
Kind code	B2
Filing date	Jul 25, 2017
Priority date	Jul 15, 2015
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

First claim

What is claimed is:

1. An integrated circuit, comprising: a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface configured to electrically connect the integrated circuit to a circuit board; a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors; and a passive device integrated in the integrated circuit, wherein the passive device is positioned between the first surface and the second surface of the substrate, the passive device comprises a thin film inductor comprising a coiled inductor coupled to at least two conductors, and wherein a majority of the coiled inductor lies within a single plane;
the passive device comprises at least a third electrical conductor positioned on a first side of the passive device, wherein the passive device comprises at least a fourth electrical conductor positioned on a second side of the passive device, and wherein the second side of the device is positioned opposite the first side of the device;
wherein the passive device is coupled to the first surface of the substrate using the third electrical conductor and the passive device is coupled to the semiconductor die using the fourth electrical conductor and the second set of electrical conductors.

2. The integrated circuit of claim 1 , wherein the passive device is embedded in the substrate.

3. The integrated circuit of claim 1 , wherein the passive device is incapable of controlling current by means of another electrical signal.

4. The integrated circuit of claim 1 , further comprising a capacitor.

5. The integrated circuit of claim 4 , wherein the capacitor comprises a multilayer capacitor.

6. The integrated circuit of claim 5 , wherein the multilayer capacitor allows different levels of capacitance to be achieved using a single multilayer capacitor.

7. The integrated circuit of claim 5 , wherein the multilayer capacitor comprises alternating conductive layers and insulating layers.

8. The integrated circuit of claim 1 , wherein the substrate further include conductors to connect the second surface of the substrate to the first surface of the substrate and devices coupled to the first and second surfaces.

9. The integrated circuit of claim 1 , wherein the passive device further includes conductors to connect the second surface of the substrate to the first surface of the substrate.

10. A method of manufacturing an integrated circuit, comprising: coupling a first set of electrical conductors to a first surface of a substrate, wherein the first set of electrical conductors electrically connect the integrated circuit to a circuit board, and wherein the substrate includes a second surface substantially opposite of the first surface; coupling a semiconductor die to the second surface of the substrate using a second set of electrical conductors; integrating a passive device into the integrated circuit, wherein the passive device is positioned between the first surface and the second surface of the substrate, the passive device comprises a thin film inductor comprising a coiled inductor coupled to at least two conductors, and wherein a majority of the coiled inductor lies within a single plane, coupling the passive device to the first surface of the substrate using a third electrical conductor positioned on a first side of the passive device; and coupling the passive device to the semiconductor die using a fourth electrical conductor positioned on a second side of the passive device and the second set of electrical conductors.

11. The method of claim 10 , wherein the passive device is incapable of controlling current by means of another electrical signal.

12. The method of claim 10 , further comprising integrating an inductor into the integrated circuit.

13. The method of claim 12 , wherein integrating the inductor into the integrated circuit comprises integrating a multilayer capacitor into the integrated circuit.

14. The method of claim 13 , wherein integrating the multilayer capacitor into the integrated circuit comprises integrating a multilayer capacitor allowing different levels of capacitance to be achieved using a single multilayer capacitor.

Assignees

• Apple Inc

Inventors

• Zhai Jun
• Ramachandran Vidhya
• Hu Kunzhong
• Pang Mengzhi
• Zhong Chonghua

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W90/00

  Package configurations · CPC title