Dual-layer bonding material process for temporary bonding of microelectronic substrates to carrier substrates

US10103048B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10103048-B2
Application numberUS-201414472073-A
CountryUS
Kind codeB2
Filing dateAug 28, 2014
Priority dateAug 28, 2013
Publication dateOct 16, 2018
Grant dateOct 16, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A process is disclosed for using two polymeric bonding material layers to bond a device wafer and carrier wafer in a way that allows debonding to occur between the two layers under low-force conditions at room temperature. Optionally, a third layer is included at the interface between the two layers of polymeric bonding material to facilitate the debonding at this interface. This process can potentially improve bond line stability during backside processing of temporarily bonded wafers, simplify the preparation of bonded wafers by eliminating the need for specialized release layers, and reduce wafer cleaning time and chemical consumption after debonding.

First claim

Opening claim text (preview).

We claim: 1. A temporary bonding method comprising: providing a stack comprising: a first substrate having a back surface and a device surface; a first bonding layer on said device surface and having an adhesion strength toward said device surface, said first bonding layer being formed of the same composition across said device surface; a second substrate having a carrier surface; and a second bonding layer on said carrier surface and having an adhesion strength toward said carrier surface, said second bonding layer being formed of the same composition across said carrier surface, wherein: said first and second substrates are bonded to one another through said first and second bonding layers; and said first and second bonding layers have an adhesion strength toward one another that is lower than said first bonding layer adhesion strength toward said device surface and lower than said second bonding adhesion strength toward said carrier surface; wherein said first and second bonding layers are each substantially free of silicones and have an adhesion strength toward one another of from about 1 psig to about 50 psig; and separating said first and second substrates. 2. The method of claim 1 , said first and second bonding layers being in contact with one another so as to form a bonding interface there between, wherein said separating results in the separation of said first and second substrates at said bonding interface. 3. The method of claim 1 , wherein said separating comprises applying a force to at least one of said first and second substrates, thereby separating said first substrate and second substrates. 4. The method of claim 3 , wherein said force is applied at a portion of the periphery of at least one of said first and second substrates, causing said one of said first and second substrates to bend at an angle away from the stack, so as to separate said first and second substrates with a peeling motion. 5. The method of claim 2 , wherein said separating comprises applying a force to at least one of said first and second substrates, thereby separating said first substrate and second substrates. 6. The method of claim 5 , wherein said force is applied at a portion of the periphery of at least one of said first and second substrates, causing said one of said first and second substrates to bend at an angle away from the stack, so as to separate said first and second substrates with a peeling motion. 7. The method of claim 1 , wherein said first bonding layer is formed directly on said device surface. 8. The method of claim 1 , wherein said second bonding layer is formed directly on said carrier surface. 9. The method of claim 1 , wherein said first bonding layer is formed directly on said device surface and said second bonding layer is formed directly on said carrier surface. 10. The method of claim 1 , further comprising a release layer between said first and second bonding layers. 11. The method of claim 10 , wherein said release layer has a thickness of from about 0.05 μm to about 5 μm. 12. The method of claim 10 , wherein said separating occurs at said release layer. 13. The method of claim 10 , wherein said release layer is formed of the same composition along substantially all of said first and second bonding layers. 14. The method of claim 1 , wherein one of said first and second bonding layers is a thermosetting layer, and the other of said first and second bonding layers is a thermoplastic layer. 15. The method of claim 1 , wherein each of said first and second bonding layers is individually formed from a composition comprising a polymer or oligomer dissolved or dispersed in a solvent system, said polymer or oligomer being selected from the group consisting of polymers and oligomers of cyclic olefins, epoxies, acrylics, silicones, styrenics, vinyl halides, vinyl esters, polyamides, polyimides, polysulfones, polyethersulfones, polyolefins, polyurethanes, polyamide esters, polyimide esters, and polyacetals. 16. The method of claim 1 , wherein said device surface comprises an array of devices selected from the group consisting of integrated circuits; MEMS; microsensors; power semiconductors; light-emitting diodes; photonic circuits; interposers; embedded passive devices; and microdevices fabricated on or from silicon, silicon-germanium, gallium arsenide, and gallium nitride. 17. The method of claim 1 , wherein said second substrate comprises a material selected from the group consisting of silicon, sapphire, quartz, metal, glass, and ceramics. 18. The method of claim 1 , said device surface comprising at least one structure selected from the group consisting of: solder bumps; metal posts; metal pillars; and structures formed from a material selected from the group consisting of silicon, polysilicon, silicon dioxide, silicon (oxy)nitride, metal, low k dielectrics, polymer dielectrics, metal nitrides, and metal silicides. 19. The method of claim 1 , wherein said providing comprises bonding said first and second substrates to one another to form said stack and subjecting said stack to processing, wherein said first and second bonding layers are bonded more strongly to one another prior to said processing than after said processing. 20. The method of claim 19 , wherein said processing is selected from the group consisting of back-grinding, chemical-mechanical polishing, etching, metal and dielectric deposition, patterning, passivation, annealing, and combinations thereof. 21. The method of claim 1 , wherein said providing comprises bonding said first and second substrates to one another to form said stack; the method further comprising subjecting said stack to processing after said providing and prior to said separating. 22. The method of claim 21 , wherein said processing selected is from the group consisting of back-grinding, chemical-mechanical polishing, etching, metal and dielectric deposition, patterning, passivation, annealing, and combinations thereof. 23. The method of claim 1 , said first and second bonding layer having an adhesion strength toward one another of from about 1 psig to about 35 psig. 24. A temporary bonding method comprising: providing a stack comprising: a first substrate having a back surface and a device surface; a first bonding layer on said device surface and having an adhesion strength toward said device surface, said first bonding layer being formed of the same composition across said device surface; a second substrate having a carrier surface; and a second bonding layer on said carrier surface and having an adhesion strength toward said carrier surface, said second bonding layer being formed of the same composition across said carrier surface, wherein: said first and second substrates are bonded to one another through said first and second bonding layers; and said first and second bonding layers have an adhesion strength toward one another that is lower than said first bonding layer adhesion strength toward said device surface and lower than said second bonding adhesion strength toward said carrier surface; wherein said first and second bonding layers are each substantially free of silicones and are in contact with one another so as to form a bonding interface there between; and separating said first and second substrates, wherein said separating results in the separation of said first and second substrates at said bonding interface.

Assignees

Inventors

Classifications

  • the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

  • Separation by peeling · CPC title

  • used to protect an active side of a device or wafer · CPC title

  • used during dicing or grinding · CPC title

  • the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10103048B2 cover?
A process is disclosed for using two polymeric bonding material layers to bond a device wafer and carrier wafer in a way that allows debonding to occur between the two layers under low-force conditions at room temperature. Optionally, a third layer is included at the interface between the two layers of polymeric bonding material to facilitate the debonding at this interface. This process can po…
Who is the assignee on this patent?
Brewer Science Inc, Brewer Science Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/74. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 16 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).