Shift register, gate driving circuit, array substrate

Patent metadata

Field	Value
Publication number	US-10102806-B2
Application number	US-201715543437-A
Country	US
Kind code	B2
Filing date	Jan 5, 2017
Priority date	Apr 26, 2016
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A shift register, comprising: a buffer discharging device which controls whether to transfer a signal of a fixed voltage terminal to an output terminal and whether to transfer the signal of the fixed voltage terminal and a signal of a second clock signal terminal to a pull-up node in accordance with a signal of an input terminal, a signal of a reset terminal and a level of a pull-down node; a holding device which controls the level of the pull-down node in accordance with the signal of the second clock signal terminal and a level of the pull-up node; an output device which controls whether to transfer a signal of a first clock signal terminal to the output terminal; a pull-down device which controls whether to transfer the signal of the fixed voltage terminal to the output terminal; a charging device which retains a level of the output terminal.

First claim

The invention claimed is:

1. A shift register, comprising a buffer discharging device, a holding device, an output device, a pull-down device, a charging device, an input terminal, a reset terminal, a first clock signal terminal, a second clock signal terminal, a fixed voltage terminal and an output terminal, wherein:
the buffer discharging device is configured to control whether to transfer a signal of the fixed voltage terminal to the output terminal and whether to transfer the signal of the fixed voltage terminal and a signal of the second clock signal terminal to a pull-up node in accordance with a signal of the input terminal, a signal of the reset terminal and a level of a pull-down node;
the holding device is configured to control the level of the pull-down node in accordance with the signal of the second clock signal terminal and a level of the pull-up node;
the output device is configured to control whether to transfer a signal of the first clock signal terminal to the output terminal in accordance with the level of the pull-up node;
the pull-down device is configured to control whether to transfer the signal of the fixed voltage terminal to the output terminal in accordance with the signal of the second clock signal terminal;
the charging device is configured to retain a level of the output terminal.

2. The shift register of claim 1 , wherein the buffer discharging device comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein:
a first electrode of the first transistor is connected to the second clock signal terminal, a second electrode of the first transistor is connected to the pull-up node, and a gate of the first transistor is connected to the input terminal;
a first electrode of the second transistor is connected to the pull-up node, a second electrode of the second transistor is connected to the first clock signal terminal, and a gate of the second transistor is connected to the reset terminal;
a first electrode of the third transistor is connected to the pull-up node, a second electrode of the third transistor is connected to the fixed voltage terminal, and a gate of the third transistor is connected to the pull-down node;
a first electrode of the fourth transistor is connected to the output terminal, a second electrode of the fourth transistor is connected to the fixed voltage terminal, and a gate of the fourth transistor is connected to the pull-down node.

3. The shift register of claim 2 , wherein the holding device comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, wherein:
a first electrode of the fifth transistor is connected to the second clock signal terminal, a second electrode of the fifth transistor is connected to the pull-down node, and a gate of the fifth transistor is connected to a first electrode of the seventh transistor and a second electrode of the eighth transistor;
a first electrode of the sixth transistor is connected to the pull-down node, a second electrode of the sixth transistor is connected to the fixed voltage terminal, and a gate of the sixth transistor is connected to the pull-up node;
the first electrode of the seventh transistor is connected to the gate of the fifth transistor, a second electrode of the seventh transistor is connected to the fixed voltage terminal, and a gate of the seventh transistor is connected to the pull-up node;
a first electrode of the eighth transistor is connected to the second clock signal terminal, the second electrode of the eighth transistor is connected to the gate of the fifth transistor, and a gate of the eighth transistor is connected to the second clock signal terminal.

4. The shift register of claim 3 , wherein the output device comprises a ninth transistor, wherein:
a first electrode of the ninth transistor is connected to the first clock signal terminal, a second electrode of the ninth transistor is connected to the output terminal, and a gate of the ninth transistor is connected to the pull-up node.

5. The shift register of claim 4 , wherein the pull-down device comprises a tenth transistor, wherein:
a first electrode of the tenth transistor is connected to the output terminal, a second electrode of the tenth transistor is connected to the fixed voltage terminal, and a gate of the tenth transistor is connected to the second clock signal terminal.

6. The shift register of claim 5 , wherein the charging device comprises a storage capacitor, wherein:
a first terminal of the storage capacitor is connected to the pull-up node, a second terminal of the storage capacitor is connected to the output terminal.

7. The shift register of claim 6 , wherein,
all the transistors are N type transistors; or
all the transistors are P type transistors.

8. A gate driving circuit, comprising:
a plurality of cascaded shift transistors, each of the shift transistors is the shift register of claim 1 .

9. The gate driving circuit of claim 8 , further comprises a first control line, a second control line, a fixed voltage line, wherein:
the first control line is connected to the first clock signal terminals of all the shift registers at odd stages and the second clock signal terminals of all the shift registers at even stages;

the second control line is connected to the first clock signal terminals of all the shift registers at even stages and the second clock signal terminals of all the shift registers at odd stages;
the fixed voltage line is connected to the fixed voltage terminal of each of the shift registers;
the pull-up node of each of the shift registers is connected to the reset terminal of the shift register at a previous stage and the input terminal of the shift register at a next stage.

10. The gate driving circuit of claim 9 , wherein a separate signal is input into the input terminal of the shift register at a first stage, and another separate signal is input into the reset terminal of the shift register at a last stage.

11. The gate driving circuit of claim 9 , wherein the buffer discharging device of the shift register comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein:
a first electrode of the first transistor is connected to the second clock signal terminal, a second electrode of the first transistor is connected to the pull-up node, and a gate of the first transistor is connected to the input terminal;
a first electrode of the second transistor is connected to the pull-up node, a second electrode of the second transistor is connected to the first clock signal terminal, and a gate of the second transistor is connected to the reset terminal;
a first electrode of the third transistor is connected to the pull-up node, a second electrode of the third transistor is connected to the fixed voltage terminal, and a gate of the third transistor is connected to the pull-down node;
a first electrode of the fourth transistor is connected to the output terminal, a second electrode of the fourth transistor is connected to the fixed voltage terminal, and a gate of the fourth transistor is connected to the pull-down node.

12. The gate driving circuit of claim 11 , wherein the holding device of the shift register comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, wherein:
a first electrode of the fifth transistor is connected to the second clock signal terminal, a second electrode of the fifth transistor is connected to the pull-down node, and a gate of the fifth transistor is connected to a first electrode of the seventh transistor and a second electrode of the eighth transistor;
a first electr

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Chen Huabin

Classifications

• G09G3/344

  based on particles moving in a fluid or in a gas, e.g. electrophoretic devices (electrophoretic devices per se G02F1/167) · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title