Shift register, its driving method, gate driver circuit and display device

Patent metadata

Field	Value
Publication number	US-9791968-B2
Application number	US-201615306264-A
Country	US
Kind code	B2
Filing date	Jan 27, 2016
Priority date	Sep 6, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

The present disclosure provides a shift register, its driving method, a gate driver circuit and a display device. The shift register includes an input module, a resetting module, a touch switching module, a node control module, a first output module and a second output module. In the shift register, through the cooperation of the above six modules, it is able to provide a touch stage between any two adjacent time periods of a display stage, it enables a driving signal output end of the shift register to output a DC signal at the touch stage, and enable the gate driver circuit to achieve a display function after the touch stage is ended.

First claim

What is claimed is:

1. A shift register, comprising an input module, a resetting module, a touch switching module, a node control module, a first output module and a second output module, wherein
a first end of the input module is configured to receive an input signal, a second end of the input module is configured to receive a first clock signal, and a third end of the input module is connected to a first node;
the input module is configured to enable the first node to be at a first potential in the case that the input signal and the first clock signal are both at the first potential;
a first end of the resetting module is configured to receive a resetting signal, a second end of the resetting module is configured to receive a third clock signal, and a third end of the resetting module is connected to the first node;
the resetting module is configured to enable the first node to be at the first potential in the case that the resetting signal and the third clock signal are both at the first potential;
a first end of the touch switching module is configured to receive a first touch-control signal, a second end of the touch switching module is connected to the first node, and a third end of the touch switching module is connected to a second node;
the touch switching module is configured to, under the control of the first touch-control signal, enable the first node to be electrically connected to the second node at a display stage, and enable the first node to be electrically disconnected from the second node at a touch stage;
a first end of the node control module is configured to receive a direct current (DC) signal, a second end of the node control module is configured to receive a fourth clock signal, a third end of the node control module is configured to receive a second touch-control signal, a fourth end of the node control module is connected to the first node, a fifth end of the node control module is connected to the second node, and a sixth end of the node control module is connected to a third node;
the node control module is configured to apply the DC signal to the first node in the case that the third node is at the first potential, apply the fourth clock signal to the third node in the case that the fourth clock signal is at the first potential, apply the second touch-control signal to the third node in the case that the second node is at the first potential, and maintain a voltage difference between the first end of the node control module and the third node to be a voltage difference within a previous time period in the case that the third node is in a floating state;
a first end of the first output module is connected to the second node, a second end of the first output module is configured to receive a second clock signal, and a third end of the first output module is connected to a driving signal output end of the shift register;
the first output module is configured to apply the second clock signal to the driving signal output end in the case that the second node is at the first potential, and maintain a voltage difference between the second node and the driving signal output end to be the voltage difference within the previous time period in the case that the second node is in the floating state;
a first end of the second output module is connected to the third node, a second end of the second output module is configured to receive the DC signal, and a third end of the second output module is connected to the driving signal output end;
the second output module is configured to apply the DC signal to the driving signal output end in the case that the third node is at the first potential;
in the case that a valid pulse signal of the input signal is at a high potential, the first potential is a high potential, the DC signal is at a low potential, and the second touch-control signal is at a low potential at the display stage and at a high potential at the touch stage; and
in the case that the valid pulse signal of the input signal is at a low potential, the first potential is a low potential, the DC signal is at a high potential, and the second touch-control signal is at the high potential at the display stage and at the low potential at the touch stage.

2. The shift register according to claim 1 , further comprising a third output module,
a first end of the third output module is configured to receive a third touch-control signal, a second end of the third output module is configured to receive the DC signal, and a third end of the third output module is connected to the driving signal output end,
wherein the third output module is configured to apply the DC signal to the driving signal output end at the touch stage under the control of the third touch-control signal.

3. The shift register according to claim 1 , wherein
the input module comprises a first switch transistor, a drain electrode of the first switch transistor is connected to the first node; and
a gate electrode of the first switch transistor is configured to receive the input signal and a source electrode of the first switch transistor is configured to receive the first clock signal, or the gate electrode of the first switch transistor is configured to receive the first clock signal and the source electrode of the first switch transistor is configured to receive the input signal.

4. The shift register according to claim 1 , wherein
the resetting module comprises a second switch transistor, a drain electrode of the second switch transistor is connected to the first node; and
a gate electrode of the second switch transistor is configured to receive the resetting signal and a source electrode of the second switch transistor is configured to receive the third clock signal, or the gate electrode of the second switch transistor is configured to receive the third clock signal and the source electrode of the second switch transistor is configured to receive the resetting signal.

5. The shift register according to claim 1 , wherein the touch switching module comprises a third switch transistor, a gate electrode of the third switch transistor is configured to receive the first touch-control signal, a source electrode of third switch transistor is connected to the first node, and a drain electrode of third switch transistor is connected to the second node.

6. The shift register according to claim 1 , wherein the node control module comprises a fourth switch transistor, a fifth switch transistor, a sixth switch transistor and a first capacitor;
a gate electrode of the fourth switch transistor is connected to the third node, a source electrode of the fourth switch transistor is configured to receive the DC signal, and a drain electrode of the fourth switch transistor is connected to the first node;
a gate electrode and a source electrode of the fifth switch transistor are configured to receive the fourth clock signal, and a drain electrode of the fifth switch transistor is connected to the third node;
a gate electrode of the sixth switch transistor is connected to the second node, a source electrode of the sixth switch transistor is configured to receive the second touch-control signal, and a drain electrode of the sixth switch transistor is connected to the third node; and
one end of the first capacitor is connected to the third node, and the other end of the first capacitor is configured to receive the DC signal.

7. The shift register according to claim 1 , wherein the first output module comprises a seventh switch transistor and a second capacitor;
a gate electrode of the seventh switch transistor is connected to the second node, a source electrode of the seventh switch transistor is configured to receive the second clock signal, and a drain electrode of the seventh switch transistor is co

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Hu Like

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G5/003

  Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092) · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title