Multiple core computer processor with globally-accessible local memories

Patent metadata

Field	Value
Publication number	US-10102179-B2
Application number	US-201615243634-A
Country	US
Kind code	B2
Filing date	Aug 22, 2016
Priority date	Oct 28, 2011
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

First claim

What is claimed is:

1. A multi-core computer processor comprising:
a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture;
a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores;
a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores; and
an independent control plane comprising direct message queues between the plurality of processor cores, wherein the independent control plane is to perform synchronization and enforce memory consistency between the plurality of memories.

2. The multi-core computer processor of claim 1 , wherein the independent control plane is configured to designate an order of transmission for specially identified messages, wherein the specially identified messages are received in the order and indicate synchronization information.

3. The multi-core computer processor of claim 1 , wherein the plurality of memories comprises a plurality of local scratch pad memories.

4. The multi-core computer processor of claim 1 , wherein the plurality of memories comprises a plurality of L1 memories.

5. The multi-core computer processor of claim 1 , wherein the plurality of memories comprises a plurality of L2 memories.

6. The multi-core computer processor of claim 1 , wherein the plurality of memories is software-managed and the plurality of caches is automatically managed.

7. The multi-core computer processor of claim 1 , wherein each of the plurality of memories is associated with one and only one of the plurality of processor cores.

8. The multi-core computer processor of claim 1 , wherein each of the plurality of memories are physically separate and located in a different location.

9. The multi-core computer processor of claim 1 , wherein each of the plurality of processor cores is configured to be able to address a main memory visible in the global memory address space via its respective cache memory.

10. The multi-core computer processor of claim 1 , wherein each of the plurality of processor cores is configured to be able to address two or more of the plurality of memories via an asynchronous direct memory access (DMA) process that allows a data copy to be transmitted directly from the memory of the processor core to a memory of another processor core.

11. The multi-core computer processor of claim 1 , wherein each of the plurality of processor cores is configured to be able to address a main memory via an asynchronous direct memory access (DMA) mechanism that allows a data copy to be transmitted directly from the memory of the processor core to the main memory.

12. The multi-core computer processor of claim 1 , wherein each of the plurality of processor cores comprises at least one register and a message queue, wherein data in a register of any of the plurality of processor cores can be transmitted to a message queue of any other of the plurality of processor cores, wherein the any other of the plurality of processor cores is a receiving core.

13. The multi-core computer processor of claim 12 , wherein the receiving core is configured to be able to read the message queue of the receiving one.

14. The multi-core computer processor of claim 12 , wherein the receiving core is configured to indicate that the receiving core has received the data and is configured to indicate a number of data items in the message queue of the receiving core.

15. The multi-core computer processor of claim 14 , wherein indicated by the receiving core is interrupt-driven, wherein the receiving core is configured to be interrupted when the receiving core receives the data.

16. The multi-core computer processor of claim 14 , wherein indicating by the receiving core is polled, wherein the receiving core is configured to be able to determine when to check for availability of the data in the message queue of the receiving core.

17. A method of using a multi-core computer processor, the method comprising:
storing cache data in at least one of a plurality of caches, each of the plurality of caches being associated with one and only one of a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture;
storing memory data in at least one of a plurality of memories, the plurality of memories supporting Partitioned Global Address Spaces (PGAS), each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores;
retrieving, by a first processor core of the plurality of processor cores associated with a first memory of the plurality of memories, at least a portion of the memory data is stored in a second memory of the plurality of memories associated with a second processor core of the plurality of processor cores, the second processor core being different from the first processor core and the first memory being different from the second memory; and
performing synchronization and enforcing memory consistency between the plurality of memories via an independent control plane comprising direct message queues between the plurality of processor cores.

18. A processor core comprising:
a common carrier substrate;
a plurality of processor cores on the common carrier substrate; and
a plurality of memories on the common carrier substrate, the plurality of memories supporting Partitioned Global Address Space (PGAS), each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories assigned an address space of a global memory address, wherein the assigned address space is indicated of a physical locality on the common carrier substrate; and
an independent control plane comprising direct message queues between the plurality of processor cores, wherein the independent control plane is configured to perform synchronization and enforce memory consistency between the plurality of memories.

19. The processor core of claim 18 , wherein the memories that are spatially close to one another have correspondingly numerically close address spaces.

20. A multi-core computer processor comprising:
a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture;
a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores;
a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores; and
an independent control plane to designate an order of transmission for specially identified messages, wherein the specially identified messages are received in the order and indicate synchronization information.

Assignees

• Univ California

Inventors

• Shalf John
• Donofrio David
• Oliker Leonid

Classifications

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F2212/1041

  Resource optimization · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title