Multi-core processor system, cache coherency control method, and computer product

Patent metadata

Field	Value
Publication number	US-8996820-B2
Application number	US-201213712816-A
Country	US
Kind code	B2
Filing date	Dec 12, 2012
Priority date	Jun 14, 2010
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.

First claim

What is claimed is:

1. A multi-core processor system comprising a processor configured to:
establish coherency of shared data values stored in a cache memory accessed by a plurality of cores;
detect a first thread executed by a first core among the cores;
identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores;
determine whether shared data commonly accessed by the first thread and the second th…

Assignees

• Fujitsu Ltd

Inventors

• Suzuki Takahisa
• Yamashita Koichiro
• Yamauchi Hiromasa
• Kurihara Koji

Classifications

• G06F12/0837 Primary

  Physics · mapped topic

• G06F12/0842

  Physics · mapped topic

• G06F2212/171

  Physics · mapped topic

• G06F12/0815 Primary

  Physics · mapped topic

• G06F12/0831

  Physics · mapped topic