Method and apparatus for reducing power consumption in a memory bus interface by selectively disabling and enabling sense amplifiers

Patent metadata

Field	Value
Publication number	US-10102157-B2
Application number	US-201213447583-A
Country	US
Kind code	B2
Filing date	Apr 16, 2012
Priority date	Jan 2, 2002
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A technique includes amplifying data signals from a memory bus interface. The amplified data signals are sampled, and the amplifier is selectively disabled in response to the absence of a predetermined operation occurring over the memory bus. In some embodiments of the invention, the amplification may be selectively enabled in response to the beginning of the predetermined operation over the memory bus.

First claim

What is claimed is:

1. An apparatus, comprising:
a semiconductor memory;
a sense amplifier coupled to read data from the semiconductor memory; and
a circuit to save power when data is not being read from the semiconductor memory, the circuit to:
maintain the sense amplifier enabled for a continuous time interval including a first memory access, wherein the sense amplifier is to sense data during the first memory access and is to sense data during a second memory access; and
selectively disable the sense amplifier after the second access based at least in part on a signal inactivity of a memory bus.

2. The apparatus of claim 1 , in which the circuit is to enable the sense amplifier when a read operation is detected upon initiation.

3. The apparatus of claim 1 , in which the semiconductor memory includes static dynamic random access memory.

4. The apparatus of claim 1 , in which the circuit is to enable the sense amplifier in response to a beginning of a read operation.

5. The apparatus of claim 4 , in which the circuit is to disable the sense amplifier in response to the end of the read operation.

6. The apparatus of claim 1 , in which the circuit is implemented with a sense amplifier control circuit.

7. The apparatus of claim 1 , wherein the signal inactivity comprises a signal state identifying an end of a burst read operation, and the circuit is to disable the sense amplifier based at least in part on detection of the signal state.

8. The apparatus of claim 1 , wherein the circuit is adapted to detect pauses in the sequence of accesses to save power when data is not being read from the semiconductor memory.

9. The apparatus of claim 1 , further comprising:
a processor to initiate a request to read data from the semiconductor memory.

10. The apparatus of claim 9 , further comprising:
a system bus to communicate the request with the memory bus.

11. The apparatus of claim 9 , further comprising:
the memory bus.

12. The apparatus of claim 1 , further comprising:
a memory controller to communicate the read data.

13. A chip, comprising:
a semiconductor memory; and
a memory controller to control reading data from the semiconductor memory, the memory controller including at least one sense amplifier to read data stored in the semiconductor memory, the memory controller to save power when data is not being read from the semiconductor memory, the memory controller to:
maintain the at least one sense amplifier enabled for a continuous time interval including a first memory access proceeded in time by a second memory access, wherein the sense amplifier is to sense data during the first memory access and is to sense data during the second memory access; and
selectively disable the at least one sense amplifier after the second memory access based at least in part on a signal inactivity of a memory bus.

14. The chip of claim 13 , in which the memory controller is to enable the sense amplifier when a read operation is initiated.

15. The chip of claim 13 , in which the semiconductor memory includes static dynamic random access memory.

16. The chip of claim 13 , in which the memory controller is to enable the sense amplifier in response to a beginning of a read operation.

17. The chip of claim 16 , in which the memory controller is to disable the sense amplifier in response to the end of the read operation.

18. The chip of claim 13 , in which the memory controller includes a sense amplifier control circuit to disable the sense amplifier.

19. A method comprising:
communicating data with a semiconductor memory using a memory bus,
wherein communicating the data comprises:
sensing data for a plurality of memory accesses during a continuous time interval, wherein the plurality of memory accesses comprises a first memory access and a second memory access that proceeds the first memory access in time, and the sensing comprises:
using the sense amplifier to sense data for a first access of the plurality of accesses, using the sense amplifier to sense data for a second access of the plurality of accesses, and maintaining the sense amplifier enabled during the continuous time interval; and
selectively disabling the sense amplifier after the second access based at least in part on a signal inactivity of the memory bus.

20. The method of claim 19 , further comprising enabling the sense amplifier in response to detecting a read operation.

21. The method of claim 19 , further comprising enabling the sense amplifier in response to detecting a beginning of a read operation.

22. The method of claim 19 , wherein sensing the data comprises sensing data for a plurality of read accesses.

Assignees

• Wilcox Jeffrey R
• Yosef Noam
• Intel Corp

Inventors

• Wilcox Jeffrey R
• Yosef Noam

Classifications

• G06F1/3253

  Power saving in bus · CPC title

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• Y02D10/151

  Cross-Sectional Technologies · mapped topic

• G06F13/1668

  Details of memory controller · CPC title

• G06F1/3225

  of memory devices · CPC title