Method of preparing a plan-view transmission electron microscope sample used in an integrated circuit analysis

US10101246B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10101246-B2
Application numberUS-201615241284-A
CountryUS
Kind codeB2
Filing dateAug 19, 2016
Priority dateAug 20, 2015
Publication dateOct 16, 2018
Grant dateOct 16, 2018

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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The present invention discloses a preparation method of plan-view TEM sample used in an integrated circuit analysis. The method comprises the steps of: providing a carrying slice, and fixing a chip containing a targeted structure sample and the carrying slice on a sample holder in a horizontal direction, and putting them in a process chamber of a FIB apparatus; cutting off a piece of chip structure containing a target structure sample by adopting a FIB; and welding the piece of chip structure on the flat and clean side of the carrying slice by using a nano-manipulator; after being taken out from the process chamber of the FIB apparatus, the carrying slice welded with the chip structure is adjusted to vertical direction, and is put in the process chamber of the FIB apparatus again; transferring and welding the chip structure on the TEM copper grid by using the nano-manipulator; and removing one layer or multiple layers above the preset target layer from the surface layer of the chip by using the FIB to obtain the desired plan-view TEM sample.

First claim

Opening claim text (preview).

The invention claimed is: 1. A preparation method of plan-view TEM sample used in an integrated circuit analysis, for exposing at least one of preset target regions of an integrated circuit chip with a multi-layer structure, wherein the at least one of preset target regions contains a targeted structure sample to be inspected, wherein the preparation method comprising the following steps: Step S1: providing a carrying slice, and fixing the integrated circuit chip containing the targeted structure sample and the carrying slice spaced from each other on a sample holder along a horizontal axis, and putting them in a process chamber of a focused ion beam apparatus, wherein the carrying slice has at least one flat and clean side; step S2: cutting off a piece of the integrated circuit chip containing the targeted structure sample by adopting a focused ion beam; and welding the piece of the integrated circuit chip on the flat and clean side of the carrying slice by using a nano-manipulator; wherein the focused ion beam is perpendicular to a top surface of each layer of the integrated circuit chip containing the targeted structure sample; step S3: taking the carrying slice out from the process chamber of the focused ion beam apparatus, then adjusting a direction of the carrying slice welded with the piece of the integrated circuit chip such that the focused ion bean is parallel to the top surface of each layer of the integrated circuit chip containing the target structure sample, and putting the carrying slice welded with the piece of the integrated circuit chip into the process chamber of the focused ion beam apparatus again; step S4: transferring and welding the piece of the integrated circuit chip on a TEM copper grid by using the nano-manipulator; Step S5: removing one layer or multiple layers above the preset target region from a top surface layer of the integrated circuit chip by using the focused ion beam to obtain the plan-view TEM sample, wherein the focused ion beam is parallel with the top surface of each layer of the integrated circuit chip containing the targeted structure sample. 2. The preparation method according to claim 1 , wherein when the carrying slice welded with the chip structure, after being taken out from the process chamber of the focused ion beam apparatus, is adjusted and is put in the process chamber of the focused ion beam apparatus again in the step S3, the piece of the integrated circuit chip welded on a top end of the flat and clean side of the carrying slice. 3. The preparation method according to claim 1 , wherein the piece of the integrated circuit chip containing the targeted structure sample, which is cut off in the target region by using the focused ion beam in the step S2, is square with a side length in a range from 1 μm to 10 μm. 4. The preparation method according to claim 1 , wherein a thickness of the piece of the integrated circuit chip containing the targeted structure sample, which is cut off in the target region by using the focused ion beam in the step S2, is in a range from 1 μm to 5 μm. 5. The preparation method according to claim 1 , wherein the material of the carrying slice is conductive material. 6. The preparation method according to claim 5 , wherein the material of the carrying slice is silicon. 7. The preparation method according to claim 1 , wherein the shortest distance from a top surface of the piece of the integrated circuit chip containing the targeted structure sample, which is cut off in the step S2, to a top surface of the target structure sample is in a range from 1 μm to 4 μm. 8. The preparation method according to claim 1 , wherein a horizontal projection shape of the piece of the integrated circuit chip containing the targeted structure sample, which is cut off in the step S2, is a right triangle. 9. The preparation method according to claim 8 , wherein a leg of the piece of right triangle shaped integrated circuit chip is welded together with the flat and clean side of the carrying slice. 10. The preparation method according to claim 8 , wherein the preset target region is a gate oxide layer, a contact hole layer or a metal layer.

Assignees

Inventors

Classifications

  • Electron or ion microscopes; Electron or ion diffraction tubes · CPC title

  • for preparing specimen to be viewed in microscopes or analyzed in microanalysers · CPC title

  • G01N1/286Primary

    involving mechanical work, e.g. chopping, disintegrating, compacting, homogenising (microtomes G01N1/06; pulverising in general B02C; mixing in general B01F) · CPC title

  • Preparing specimens for investigation {including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q}(mounting specimens on microscopic slides G02B21/34; means for supporting the objects or the materials to be analysed in electron microscopes H01J37/20 {; laboratory gas handling apparatus B01L5/00}) · CPC title

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What does patent US10101246B2 cover?
The present invention discloses a preparation method of plan-view TEM sample used in an integrated circuit analysis. The method comprises the steps of: providing a carrying slice, and fixing a chip containing a targeted structure sample and the carrying slice on a sample holder in a horizontal direction, and putting them in a process chamber of a FIB apparatus; cutting off a piece of chip struc…
Who is the assignee on this patent?
Shanghai Huali Microelect Corp
What technology area does this patent fall under?
Primary CPC classification G01N1/286. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 16 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).