Wafer-to-wafer alignment method

Patent metadata

Field	Value
Publication number	US-10100858-B2
Application number	US-201615337745-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Apr 26, 2012
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

A silicon alignment pin is used to align successive layer of component made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

First claim

What is claimed is:

1. A method of aligning two component layers of a multilayer device, comprising the steps of:
providing an alignment pin having a first end and a second end, said alignment pin comprising a compressible structure having a central axis, said compressible structure having an arcuate surface disposed about said central axis, said compressible structure having an aperture oriented along said central axis defined within said compressible structure, said compressible structure having two opposed projections extending continuously from the arcuate surface and apart from each other with a gap therebetween in a plane perpendicular to said central axis, said compressible structure configured to assume a relaxed configuration when no mechanical force is applied to said two opposed projections wherein said first end and second end each have a dimension d measured along a chord perpendicular to and intersecting said central axis, said chord having each of its two ends situated on said arcuate surface, and said compressible structure configured to assume a compressed configuration upon the application of a mechanical force to said two opposed projections wherein said first end and second end each have a dimension c smaller than said dimension d measured along said chord perpendicular to and intersecting said central axis, said chord having each of its two ends situated on said arcuate surface, wherein the gap is between 20 and 200 microns;
providing a first layer of a multilayer device, said first layer having a first layer aperture defined in a surface of said first layer, said first layer aperture having a dimension larger than said dimension c and smaller than said dimension d;
providing a second layer of said multilayer device, said second layer having a second layer aperture defined in a surface of said second layer, said second layer aperture having a dimension substantially equal to said first layer aperture, said second layer aperture designed to be in registry with said first layer aperture when said first layer and said second layer are aligned;
applying mechanical force to said two opposed projections of said compressible structure to provide said compressible structure in said compressed configuration;
inserting said first end of said alignment pin in said compressed configuration into said first layer aperture defined in said surface of said first layer;
releasing said mechanical force from said two opposed projections of said compressible structure, thereby mating said first end of said alignment pin with said first layer of said multilayer device; and
mating said second layer aperture of said second layer of said multilayer device with said second end of said alignment pin, thereby bringing said first layer and said second layer of said multilayer device into alignment.

2. The method of aligning two component layers of a multilayer device of claim 1 , wherein said alignment of said first layer of said multilayer device and said second layer of said multilayer device is an alignment to within 5 μm.

3. The method of aligning two component layers of a multilayer device of claim 1 , wherein at least one of one of said first layer of said multilayer device and said second layer of said multilayer device is fabricated from a semiconductor wafer.

4. The method of aligning two component layers of a multilayer device of claim 1 , wherein at least one of one of said first layer of said multilayer device and said second layer of said multilayer device is fabricated from a metal.

5. The method of aligning two component layers of a multilayer device of claim 1 , further comprising the step of securing said first layer of said multilayer device and said second layer of said multilayer device in an assembled state.

Assignees

• California Inst Of Techn

Inventors

• Jung-Kubiak Cecile
• Reck Theodore
• Thomas Bertrand
• Lin Robert H
• Peralta Alejandro
• Gill John J
• Lee Choonsup
• Siles Jose V
• Toda Risaku
• Chattopadhyay Goutam
• Cooper Ken B
• Mehdi Imran

Classifications

• F16B5/025 Primary

  specially designed to compensate for misalignement or to eliminate unwanted play · CPC title

• H05K13/0015

  Orientation; Alignment; Positioning · CPC title

• Y10T29/49895

  Associating parts by use of aligning means [e.g., use of a drift pin or a "fixture"] · CPC title

• Y10T403/20

  with indicator or inspection means · CPC title

• F16B19/004

  made in one piece (F16B21/084 takes precedence) · CPC title