Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10096552-B2
Application number	US-201715689861-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Jan 3, 2017
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface;
a first encapsulant encapsulating at least portions of the first semiconductor chip;
a connection member disposed on the first encapsulant and the first active surface of the first semiconductor chip and including first vias and a first redistribution layer electrically connected to the first connection pads through the first vias;
a second semiconductor chip having a second active surface having second connection pads disposed thereon, and a second inactive surface opposing the second active surface and attached to the connection member;
a second encapsulant covering at least portions of the connection member and encapsulating at least portions of the second semiconductor chip;
a second redistribution layer disposed on the second encapsulant and the second active surface of the second semiconductor chip;
second vias penetrating through the second encapsulant and electrically connecting the second connection pads and the second redistribution layer to each other; and
third vias penetrating through the second encapsulant and electrically connecting the first redistribution layer and the second redistribution layer to each other.

2. The semiconductor package of claim 1 , wherein a first region is a projected region of the first semiconductor chip projected in a direction perpendicular to the first active surface and a second region is a region surrounding the first region, and all the first connection pads connected to the first vias are redistributed to the second region through the first redistribution layer.

3. The semiconductor package of claim 1 , wherein a cut surface of the third via by a plane perpendicular to the first active surface has a taper shape.

4. The semiconductor package of claim 1 , wherein the first connection pads are arrayed on a central portion of the first active surface of the first semiconductor chip.

5. The semiconductor package of claim 1 , wherein the first connection pads are in direct contact with the first vias of the connection member.

6. The semiconductor package of claim 1 , further comprising a passivation layer disposed on the second encapsulant and the second active surface of the second semiconductor chip and covering at least portions of the second redistribution layer,
wherein the passivation layer includes openings opening portions of the second redistribution layer, and
at least one of the openings of the passivation layer is disposed on a fan-out region of the second semiconductor chip.

7. The semiconductor package of claim 6 , wherein the third vias are formed at a predetermined thickness along walls of via holes penetrating through the second encapsulant, and
the passivation layer fills spaces between the third vias of the via holes.

8. The semiconductor package of claim 1 , further comprising a die attach film (DAF), through which the second inactive surface of the second semiconductor chip is attached to the connection member.

9. The semiconductor package of claim 1 , wherein the connection member includes a first insulating layer disposed on the first encapsulant and the first active surface of the first semiconductor chip, the first redistribution layer disposed on the first insulating layer, the first vias penetrating through the first insulating layer and electrically connecting the first connection pads and the first redistribution layer to each other, and a second insulating layer disposed on the first insulating layer and covering at least portions of the first redistribution layer, and
the second inactive surface of the second semiconductor chip is attached to the second insulating layer.

10. The semiconductor package of claim 1 , further comprising a support member having a through-hole and disposed on one surface of the connection member on which the first semiconductor chip is disposed,
wherein the first semiconductor chip is disposed in the through-hole, and
the first encapsulant fills at least portions of the through-hole.

11. The semiconductor package of claim 10 , wherein the support member includes a third redistribution layer electrically connected to the first redistribution layer.

12. The semiconductor package of claim 10 , wherein the support member includes a first insulating layer, a third redistribution layer in contact with the connection member and embedded in the first insulating layer, and a fourth redistribution layer disposed on the other surface of the first insulating layer opposing one surface of the first insulating layer in which the third redistribution layer is embedded.

13. The semiconductor package of claim 12 , wherein the support member further includes a second insulating layer disposed on the first insulating layer and covering the fourth redistribution layer and a fifth redistribution layer disposed on the second insulating layer.

14. The semiconductor package of claim 10 , wherein the support member includes a first insulating layer, a third redistribution layer and a fourth redistribution layer disposed on opposite surfaces of the first insulating layer, respectively, a second insulating layer disposed on the first insulating layer and covering the third redistribution layer, and a fifth redistribution layer disposed on the second insulating layer.

15. The semiconductor package of claim 14 , wherein the support member further includes a third insulating layer disposed on the first insulating layer and covering the fourth redistribution layer and a sixth redistribution layer disposed on the third insulating layer.

16. The semiconductor package of claim 1 , wherein a length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface being a surface of the second via cut by a plane parallel to the second active surface, and the second cut surface being a surface of the third via cut by the plane parallel to the second active surface.

17. The semiconductor package of claim 1 , wherein the third vias have a diameter greater than those of the first vias and the second vias.

18. A semiconductor package comprising:
a first semiconductor chip having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface;
a first encapsulant encapsulating at least portions of the first semiconductor chip;
a second semiconductor chip having a second active surface having second connection pads disposed thereon, and a second inactive surface opposing the second active surface;
a connection member disposed between the first encapsulant and the first active surface of the first semiconductor chip, and the second encapsulant and the second inactive surface of the second semiconductor chip, the connection member including a first insulating layer, first vias penetrating through the first insulating layer and being in contact with the first connection pads of the first semiconductor chip, and a first redistribution layer electrically connected to the first connection pads through the first vias;
a second encapsulant covering at least portions of the connection member and encapsulating at least portions of the second semiconductor chip;
a second redistribution layer disposed on the second encapsulant and the second active surface of the second semiconductor chip;
second vias penetrating

Assignees

• Samsung Electro Mech

Inventors

• Kim Han
• Jo Eun Jung
• Shim Jung Ho

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title