Packaged semiconductor die and CTE-engineering die pair

Patent metadata

Field	Value
Publication number	US-10096535-B2
Application number	US-201113995479-A
Country	US
Kind code	B2
Filing date	Dec 21, 2011
Priority date	Dec 21, 2011
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a bumpless build-up layer (BBUL) substrate comprising an encapsulant layer and a plurality of build-up layers;
a semiconductor die embedded in the BBUL substrate and having a surface area; and
a CTE-engineering die embedded in the BBUL substrate and bonded to the semiconductor die, and having a surface area the same and in alignment with the surface area of the semiconductor die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.

2. The semiconductor package of claim 1 , wherein the semiconductor die comprises silicon, and the CTE-engineering die comprises copper.

3. The semiconductor package of claim 1 , wherein the CTE-engineering die is, or is greater than, approximately 5 times as thick as the semiconductor die.

4. The semiconductor package of claim 3 , wherein the semiconductor die has a thickness of approximately 20 microns, and the CTE-engineering die has a thickness of approximately 100 microns.

5. The semiconductor package of claim 1 , wherein the CTE-engineering die is bonded to the semiconductor die by a eutectic gold (Au) and tin (Sn) solder.

6. The semiconductor package of claim 1 , wherein the semiconductor die and the CTE-engineering die are housed in a core of the substrate.

7. The semiconductor package of claim 1 , wherein the substrate is a coreless substrate.

8. A method of fabricating a semiconductor package, the method comprising:
thinning a semiconductor wafer from a backside of the semiconductor wafer; and, subsequently, bonding, via the backside, the semiconductor wafer to a CTE-engineering wafer or panel; and, subsequently,
singulating the semiconductor wafer and the CTE-engineering wafer or panel to form a plurality of semiconductor die and CTE-engineering die pairs; and, subsequently,
packaging a semiconductor die and CTE-engineering die pair in a single package, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.

9. The method of claim 8 , wherein coupling the semiconductor wafer to the CTE-engineering wafer or panel comprises bonding a silicon wafer to a copper wafer or panel.

10. The method of claim 8 , wherein thinning the semiconductor wafer comprises thinning to a thickness of approximately one fifth the thickness of the CTE-engineering wafer or panel.

11. The method of claim 8 , wherein thinning the semiconductor wafer comprises thinning to a thickness of approximately 20 microns.

12. The method of claim 8 , wherein bonding the semiconductor wafer to the CTE-engineering wafer or panel comprises using a eutectic gold (Au) and tin (Sn) solder.

13. A semiconductor package, comprising:
a bumpless build-up layer (BBUL) substrate having a land side, the BBUL substrate comprising an encapsulant layer and a plurality of build-up layers;
a semiconductor die embedded in the (BBUL) substrate, the semiconductor die comprising an active side proximate to the land side of the (BBUL) substrate, and comprising a back side having a surface area distal from the land side of the (BBUL) substrate; and
a CTE-engineering die embedded in the (BBUL) substrate and bonded to the semiconductor die, the CTE-engineering die having a surface area the same and in alignment with the surface area of the back side of the semiconductor die, wherein the CTE of the CTE-engineering die dominates a combined CTE of the semiconductor die and the CTE-engineering die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.

14. The semiconductor package of claim 13 , wherein the semiconductor die comprises silicon, and the CTE-engineering die comprises copper.

15. The semiconductor package of claim 13 , wherein the CTE-engineering die is, or is greater than, approximately 5 times as thick as the semiconductor die.

16. The semiconductor package of claim 15 , wherein the semiconductor die has a thickness of approximately 20 microns, and the CTE-engineering die has a thickness of approximately 100 microns.

17. The semiconductor package of claim 13 , wherein the CTE-engineering die is bonded to the semiconductor die by a eutectic gold (Au) and tin (Sn) solder.

18. The semiconductor package of claim 13 , wherein the semiconductor die and the CTE-engineering die are housed in a core of the substrate.

19. The semiconductor package of claim 13 , wherein the substrate is a coreless substrate.

20. A semiconductor package, comprising:
a substrate;
a semiconductor die coupled to the substrate and having a surface area; and
a CTE-engineering die bonded to the semiconductor die, and having a surface area the same and in alignment with the surface area of the semiconductor die, wherein the CTE-engineering die has flat sidewalls flush with flat sidewalls of the semiconductor die, wherein the CTE-engineering die comprises a metal, and wherein the CTE-engineering die has a CTE different than a CTE of the semiconductor die.

21. The semiconductor package of claim 20 , wherein the semiconductor die comprises silicon, and the CTE-engineering die comprises copper.

22. The semiconductor package of claim 20 , wherein the CTE-engineering die is, or is greater than, approximately 5 times as thick as the semiconductor die.

23. The semiconductor package of claim 22 , wherein the semiconductor die has a thickness of approximately 20 microns, and the CTE-engineering die has a thickness of approximately 100 microns.

24. The semiconductor package of claim 20 , wherein the CTE-engineering die is bonded to the semiconductor die by a eutectic gold (Au) and tin (Sn) solder.

Assignees

• Hu Chuan
• Intel Corp

Inventors

• Hu Chuan

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title