Direct plasma densification process and semiconductor devices

Patent metadata

Field	Value
Publication number	US-10096513-B2
Application number	US-201715619283-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Dec 26, 2013
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising at least one feature having a critical dimension in the range of about 5 nanometers (nm) to less than about 30 nm;
an underlayer on the substrate, the underlayer comprising an upper surface, lower surface, and first and second side surfaces;
a barrier layer comprising a nitride on the underlayer; and
a fin on the substrate;

wherein:
nitrogen is present in said underlayer to a depth of less than 5 nm from said upper surface, lower surface, or first or second side surfaces;
said barrier layer has a first thickness of greater than 0 to less than or equal to 2 nanometers (nm);
at least a portion of said underlayer is disposed on said fin; and
at least a portion of the barrier layer is disposed on at least the portion of the underlayer that is disposed on said fin.

2. The semiconductor device of claim 1 , wherein the first thickness is greater than 0 to less than or equal to 1 nm.

3. The semiconductor device of claim 1 , wherein the nitride comprises a metal nitride.

4. The semiconductor device of claim 3 , wherein:
the barrier layer comprises titanium nitride; and
the underlayer comprises titanium.

5. The semiconductor device of claim 4 , wherein:
said underlayer has a second thickness between the upper and lower surfaces or between the first and second side surfaces; and
said second thickness is greater than 5 nm.

6. The semiconductor device of claim 1 , wherein the underlayer comprises a metal.

7. The semiconductor device of claim 1 , wherein at least a portion of the underlayer does not contain nitrogen.

8. The semiconductor device of claim 1 , further comprising a gate dielectric layer, wherein at least a portion of the gate dielectric layer is between said underlayer and said fin.

9. The semiconductor device of claim 8 , further comprising a work function material (WFM) layer, wherein at least a portion of the WFM layer is between the gate dielectric layer and said underlayer.

10. The semiconductor device of claim 8 , wherein the WFM layer is a layer of an NMOS or PMOS work function material.

11. The semiconductor device of claim 10 , wherein the barrier layer comprises titanium nitride.

12. The semiconductor device of claim 1 , wherein said underlayer comprises a work function material (WFM).

13. The semiconductor device of claim 12 , wherein the barrier layer comprises titanium nitride.

14. The semiconductor device of claim 1 , further comprising an interlayer dielectric on the substrate, the interlayer dielectric comprising an interconnect trench comprising at least one wall, wherein at least a portion of the underlayer is disposed on at least a portion of the wall of the interconnect trench and at least a portion of the barrier layer is disposed on the portion of the underlayer that is on the wall of the interconnect trench.

15. The semiconductor device of claim 12 , wherein the barrier layer comprises titanium nitride.

16. The semiconductor device of claim 1 , further comprising an interlayer dielectric on the substrate, the interlayer dielectric comprising an contact opening, wherein at least a portion of the underlayer is disposed on the contact opening, and at least a portion of the barrier layer is disposed on the portion of the underlayer that is on the contact opening.

17. The semiconductor device of claim 16 , wherein the barrier layer comprises titanium nitride.

18. The semiconductor device of claim 1 , wherein the semiconductor device is a tri-gate transistor.

19. The semiconductor device of claim 14 , wherein the semiconductor device is a tri-gate transistor.

20. The semiconductor device of claim 16 , wherein the semiconductor device is a tri-gate transistor.

21. A semiconductor device, comprising:
a substrate comprising at least one feature having a critical dimension in the range of about 5 nanometers (nm) to less than about 30 nm;
an underlayer comprising titanium on the substrate, the underlayer comprising an upper surface, lower surface, and first and second side surfaces;
a barrier layer comprising titanium nitride on the underlayer;

wherein:
nitrogen is present in said underlayer to a depth of less than 5 nm from said upper surface, lower surface, or first or second side surfaces; and
said barrier layer has a first thickness of greater than 0 to less than or equal to 2 nanometers (nm);
said underlayer has a second thickness between the upper and lower surfaces or between the first and second side surfaces; and
said second thickness is greater than 5 nm.

Assignees

• Intel Corp

Inventors

• Farmer Jason A
• Leib Jeffrey S
• Bergstrom Daniel B

Classifications

• H10P14/432

  using selective deposition · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/055

  by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition · CPC title

• H10W20/43

  Layouts of interconnections · CPC title