Method of fabricating a packaging substrate including a carrier having two carrying portions

Patent metadata

Field	Value
Publication number	US-10096491-B2
Application number	US-201514755372-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Aug 22, 2012
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.

First claim

What is claimed is:

1. A method of fabricating a packaging substrate, comprising:
providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side with a first metal layer and a second metal layer formed on an entirety of the first side and an entirety of the second side, respectively, and the carrying portions being bonded together through the second sides thereof, wherein the carrying portions are bonded through the second metal layers with the second metal layers being in direct contact with each other;
after providing the carrier, forming a preliminary metal layer on each of the first metal layers;
after forming the preliminary metal layer on each of the first metal layers, forming a single circuit layer from each of the preliminary metal layers on the first side of each of the carrying portions, wherein the single circuit layer is in direct contact with the first metal layer; and
after forming the single circuit layer from each of the preliminary metal layers on the first side of each of the carrying portions, separating the carrying portions from each other to form two packaging substrates, wherein the first metal layer and the second metal layer are intact after forming the two packaging substrates.

2. The method of claim 1 , wherein the first metal layer and the second metal layer are made of copper foil.

3. The method of claim 1 , wherein the second metal layers of the carrying portions are bonded by vacuum lamination.

4. The method of claim 1 , wherein the step of forming the circuit layer further comprises:
forming a resist layer on the preliminary metal layer, and then forming a plurality of openings in the resist layer for exposing a portion of the preliminary metal layer;
removing the exposed portion of the preliminary metal layer; and
removing the resist layer.

5. The method of claim 4 , wherein the preliminary metal layer is laminated on the first metal layer.

Assignees

• Siliconware Precision Industries Co Ltd
• Silicon Prec Industries Co Ltd

Inventors

• Pai Yu-Cheng
• Lin Chun-Hsien
• Hsiao Wei-Chung
• Sun Ming-Chen
• Hung Liang-Yi

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title