Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10096490-B2
Application number	US-201715674449-A
Country	US
Kind code	B2
Filing date	Aug 10, 2017
Priority date	Nov 10, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

First claim

We claim:

1. A method of manufacturing semiconductor devices that each includes a plurality of conductive routing layers, comprising:
obtaining an etched and plated leadframe that includes a plurality of copper routing circuits and a plurality of package terminals, wherein the plurality of copper routing circuits forms a copper leadframe routing layer;
forming at least one conductive ink printed routing layer on top of the copper leadframe routing layer, wherein each of the at least one conductive ink printed routing layer is formed by:
coupling a plurality of interconnections with routing circuits associated with a previous routing layer that is directly beneath a current conductive ink printed routing layer being formed;
forming an intermediary insulation layer on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has the natural surface roughness;
performing an abrasion procedure to roughen at least the top surface of the intermediary insulation layer such that, after the abrasion procedure, the top surface of the intermediary insulation layer has an unnatural surface roughness that is rougher than the natural surface roughness; and
adhering a conductive ink layer on the roughened top surface of the intermediary insulation layer to form a plurality of conductive ink routing circuits that is included in the current conductive ink printed routing layer;

coupling a plurality of dies with a topmost conductive ink printed routing layer;
encapsulating the plurality of dies and the topmost conductive ink printed routing layer with a topmost insulation layer;
etching away exposed copper at the bottom of the leadframe, thereby isolating the plurality of package terminals and exposing the plurality of copper routing circuits at the bottom of the leadframe;
encapsulating the plurality of exposed copper routing circuits at the bottom of the leadframe with a bottommost insulation layer; and
performing a cut-through procedure to singulate the semiconductor packages from each other.

2. The method of claim 1 , wherein obtaining an etched and plated leadframe includes:
etching a copper substrate to form the plurality of copper routing circuits at a top surface of the copper substrate; and
plating a plurality of areas on surfaces of the copper substrate, thereby resulting in the etched and plated leadframe, wherein the plurality of areas includes bottom plated areas that eventually form the plurality of package terminals and includes top plated areas that are on the plurality of copper routing circuits.

3. The method of claim 2 , wherein the abrasion procedure includes:
coating at least the top surface of the intermediary insulation layer with an adhesion promoter material;
heating the leadframe such that the adhesion promoter material reacts with a portion of the intermediary insulation layer; and
etching away a baked film, resulting in the top surface of the intermediary insulation layer having the unnatural surface roughness that is rougher than the natural surface roughness.

4. The method of claim 3 , wherein each of the at least one conductive ink printed routing layer is further formed by, after performing an abrasion procedure and before adhering a conductive ink layer on the roughened top surface:
printing a catalyst material on the roughened top surface of the intermediary insulation layer, wherein the printing of the catalyst material forms a structure of the plurality of conductive ink routing circuits.

5. The method of claim 4 , wherein adhering a conductive ink layer on the roughened top surface includes:
using a conductive ink; and
transforming the conductive ink to conductive solid, wherein the adhesion of the conductive ink layer with the intermediary insulation layer having the unnatural surface roughness is better than the adhesion of the conductive ink layer with the intermediary insulation layer having the natural surface roughness.

6. The method of claim 5 , wherein each of the at least one conductive ink printed routing layer is further formed by, after adhering a conductive ink layer on the roughened top surface, obtaining a desired thickness of the conductive ink routing circuits whereby conductive ink is printed on conductive ink.

7. The method of claim 6 , wherein the desired thickness of the conductive ink routing circuits is obtained via a printing process, wherein the printing process includes repeating the printing a catalyst material step and the adhering step in one or more loops.

8. A method of manufacturing semiconductor devices that each includes a plurality of conductive routing layers, comprising:
obtaining an etched and plated leadframe that includes a plurality of copper routing circuits and a plurality of package terminals, wherein the plurality of copper routing circuits forms a copper leadframe routing layer;
forming at least one conductive ink printed routing layer on top of the copper leadframe routing layer, wherein each of the at least one conductive ink printed routing layer is formed by:
coupling a plurality of interconnections with routing circuits associated with a previous routing layer that is directly beneath a current conductive ink printed routing layer being formed;
forming an intermediary insulation layer on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer that has the natural surface roughness;
performing an abrasion procedure to roughen at least the top surface of the intermediary insulation layer such that, after the abrasion procedure, the top surface of the intermediary insulation layer has an unnatural surface roughness that is rougher than the natural surface roughness; and
adhering a conductive ink layer on the roughened top surface of the intermediary insulation layer to form a plurality of conductive ink routing circuits that is included in the current conductive ink printed routing layer, wherein adhering a conductive ink layer includes printing conductive ink on the intermediary insulation layer and transforming the conductive ink on the intermediary insulation layer to a conductive solid;

coupling a plurality of dies with a topmost conductive ink printed routing layer;
encapsulating the plurality of dies and the topmost conductive ink printed routing layer with a topmost insulation layer;
etching away exposed copper at the bottom of the leadframe, thereby isolating the plurality of package terminals and exposing the plurality of copper routing circuits at the bottom of the leadframe;
encapsulating the plurality of exposed copper routing circuits at the bottom of the leadframe with a bottommost insulation layer; and
performing a cut-through procedure to singulate the semiconductor packages from each other.

9. The method of claim 8 , wherein the conductive ink includes powdered or flaked silver and carbon-like materials.

10. The method of claim 8 , wherein the abrasion procedure includes:
coating at least the top surface of the intermediary insulation layer with an adhesion promoter material;
heating the leadframe such that the adhesion promoter material reacts with a portion of the intermediary insulation layer; and
etching away a baked film, resulting in the top surface of the intermediary insulation layer having the unnatural surface roughness that is rougher than the natural surface roughness.

11. The method of claim 8 , wherein each of the at least one conductive ink printed routing layer is further formed by, after performing an abrasion procedure and before adhering a conductive ink layer on the roughened top

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Sirinorakul Saravuth
• Yenrudee Suebphong

Classifications

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/457

  of metallic layers on leadframes · CPC title