Secure processor and a program for a secure processor

Patent metadata

Field	Value
Publication number	US-10095890-B2
Application number	US-201615340065-A
Country	US
Kind code	B2
Filing date	Nov 1, 2016
Priority date	Jun 30, 2004
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

First claim

The invention claimed is:

1. A processor comprising:
a translation look aside buffer including a plurality of table entries, each of the table entries including fields for a logical address, a physical address corresponding to the logical address, a context identifier identifying a context with which the logical address is associated, and a first flag indicating whether an address space associated with the context is secure;
an execution circuit configured to execute execution codes corresponding to a plurality of contexts and to output a logical address associated with a current context among the plurality of contexts, the output logical address matching the logical address of a particular one of the plurality of table entries;
a mode register configured to indicate whether the execution circuit is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited; and
a memory access control circuit configured to:
receive the output logical address;
determine whether the context identifier of the particular one of the table entries matches a reference context identifier of the current context and whether the first flag of the particular one of the plurality of table entries is set to a first state indicating that the address space associated with the context is secure; and
when the execution circuit is in the first mode, the context identifier of the particular one of the plurality of table entries matches the reference context identifier, and the first flag of the particular one of the plurality of table entries is set to the first state, output the physical address of the particular one of the table entries by referring to the translation look aside buffer.

2. The processor according to claim 1 , wherein
each of the table entries includes a second flag indicating whether an address space associated with a context has been authenticated, the memory access control unit being configured to:
determine whether the second flag of the particular one of the table entries is set to a second state indicating that the address space associated with the context has been authenticated; and
output the physical address of the particular one of the table entries when the second flag of the particular one of the table entries is set to the second state.

3. The processor according to claim 2 , wherein the memory access control circuit is
configured to:
determine whether the current context is a secure context; and
when the current context is a secure context, determine whether a secure context identifier of the particular one of the table entries matches a reference secure context identifier of the secure context.

4. The processor according to claim 1 , wherein the reference context identifier is generated when a program associated with the current context is activated.

5. The processor according to claim 1 , wherein a mode switching between the first mode and the second mode is triggered by an interrupt.

6. The processor according to claim 5 , wherein the mode register is set in response to the interrupt.

7. The processor according to claim 1 , wherein the first mode includes a secure mode and the second mode includes a normal mode.

8. The processor according to claim 1 , wherein the context identifier is associated with one of a normal process and a secure process.

9. The processor according to claim 1 , wherein the context identifier identifies a process type with which the logical address is associated.

10. The processor according to claim 9 , wherein the process type is secure or non-secure.

11. A processor comprising:
a translation look aside buffer including a plurality of table entries, each of the table entries including fields for a logical address, a physical address corresponding to the logical address, a context identifier identifying a context with which the logical address is associated, and a first flag indicating whether an address space associated with the context is secure;
an execution circuit configured to execute execution codes corresponding to a plurality of contexts and to output a logical address associated with a current context among the plurality of contexts, the output logical address matching the logical address of a particular one of the plurality of table entries; and
a mode register configured to indicate whether the execution circuit is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited;
wherein, when the execution circuit is in the first mode, the context identifier of the particular one of the plurality of table entries matches a reference context identifier of the current context, and the first flag of the particular one of the plurality of table entries is set to a first state indicating that the address space associated with the context is secure, the physical address of the particular one of the table entries is output by referring to the translation look aside buffer.

12. The processor according to claim 11 , wherein
each of the table entries includes a second flag indicating whether an address space associated with a context has been authenticated, and
when the second flag of the particular one of the table entries is set to a second state indicating that the address space associated with the context has been authenticated, the physical address of the particular one of the table entries is output.

13. The processor according to claim 12 , wherein
when the current context is a secure context, whether a secure context identifier of the particular one of the table entries matches a reference secure context identifier of the secure context is determined.

14. The processor according to claim 11 , wherein the reference context identifier is generated when a program associated with the current context is activated.

15. The processor according to claim 11 , wherein a mode switching between the first mode and the second mode is triggered by an interrupt.

16. The processor according to claim 11 , wherein the mode register is set in response to the interrupt.

17. The processor according to claim 11 , wherein the first mode includes a secure mode and the second mode includes a normal mode.

18. The processor according to claim 11 , wherein the context identifier is associated with one of a normal process and a secure process.

19. The processor according to claim 11 , wherein the context identifier identifies a process type with which the logical address is associated.

20. The processor according to claim 19 , wherein the process type is secure or non-secure.

Assignees

• Socionext Inc

Inventors

• Goto Seiji
• Kamada Jun
• Tamiya Taiji

Classifications

• G06F21/72

  in cryptographic circuits · CPC title

• G06F21/74 Primary

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

• G06F21/575

  Secure boot · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title

• G06F21/70

  Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer · CPC title