Hardware apparatuses and methods to control cache line coherence
US-2016179674-A1 · Jun 23, 2016 · US
US10095622B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10095622-B2 |
| Application number | US-201514983081-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 29, 2015 |
| Priority date | Dec 29, 2015 |
| Publication date | Oct 9, 2018 |
| Grant date | Oct 9, 2018 |
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Official abstract text for this publication.
Embodiments of systems, method, and apparatuses for remote monitoring are described. In some embodiments, an apparatus includes at least one monitoring circuit to monitor for memory accesses to an address space; at least one a monitoring table to store an identifier of the address space; and a tag directory per core used by the core to track entities that have access to the address space.
Opening claim text (preview).
We claim: 1. An apparatus comprising: at least one monitoring circuit to monitor for memory accesses to an address space; at least one a monitoring table to store an identifier of the address space; a tag directory per core used by the core to track entities that have access to the address space, wherein the tag directory is a look-up directory and wherein each row of the directory to include a memory size granularity, a hashed address, a tracking granularity, and a remote node indicator. 2. The apparatus of claim 1 , wherein the memory size granularity is one of cache line, page, large page, or huge page. 3. The apparatus of claim 1 , wherein the tracking granularity is by number of node groups. 4. The apparatus of claim 1 , wherein the remote node indicator is a Bloom filter result of nodes that have access to the address space. 5. The apparatus of claim 1 , wherein the remote node indicator is a bit mask of nodes that have access to the address space. 6. The apparatus of claim 1 , further comprising: a plurality of cores to execute instructions; caching agent circuitry to process memory requests from at least one of the plurality of cores; and home agent circuitry to process memory requests from the caching agent and as a home for part of a memory space of the apparatus. 7. The apparatus of claim 6 , wherein the caching agent circuitry and home agent circuitry are a part of the same circuit. 8. The apparatus of claim 1 , wherein the memory size granularity is one of cache line, page, large page, or huge page, the tracking granularity is by number of node groups. 9. The apparatus of claim 8 , wherein the remote node indicator is a Bloom filter result of nodes that have access to the address space. 10. The apparatus of claim 8 , wherein the remote node indicator is a bit mask of nodes that have access to the address space. 11. The apparatus of claim 1 , further comprising: caching agent circuitry to process memory requests from at least one of a plurality of cores; and home agent circuitry to process memory requests from the caching agent and as a home for part of a memory space of the apparatus. 12. The apparatus of claim 11 , wherein the caching agent circuitry and home agent circuitry are a part of the same circuit.
State-only directory, i.e. not recording identity of sharing or owning nodes · CPC title
In storage network, e.g. network attached cache · CPC title
in combination with broadcast means (e.g. for invalidation or updating) · CPC title
with dedicated cache, e.g. instruction or stack · CPC title
using directory methods · CPC title
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