Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure

Patent metadata

Field	Value
Publication number	US-10095479-B2
Application number	US-201514694890-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	Apr 23, 2015
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.

First claim

The invention claimed is:

1. One or more non-transitory computer storage media encoded with program code that when processed by a computing system causes the computing system to perform operations comprising:
instantiating, within an application software development environment, an input array, an output array, and a plurality of virtual processor instances, wherein the input array stores input image data of one or more line groups of an image, and wherein the output array stores output image data of one or more line groups of the image, wherein each virtual processor instance comprises one or more registers, each virtual processor instance being configured to execute instructions of an instruction set architecture having a load instruction that references locations within the input array of the application software development environment, and wherein each virtual processor instance is configured to execute a respective thread of a plurality of threads, wherein each thread is assigned to a respective line group position within a line group of the image;
receiving a load instruction of the instruction set architecture of the virtual processor instances, wherein the load instruction identifies a target register and specifies a load address having a source x offset and a source y offset, the source x offset and the source y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned;
executing a respective thread having the load instruction by each virtual processor instance of the plurality of virtual processor instances thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, wherein executing the load instruction includes performing operations comprising:
obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
computing a two-dimensional source position in the line group of the image including using the source x offset and the source y offset of the load address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
copying, to a target register of the virtual processor instance identified by the load instruction, data from a location in the input image array corresponding to the computed two-dimensional source position in the line group of the image.

2. The one or more computer storage media of claim 1 , wherein executing the load instruction by each virtual processor instance of the plurality of virtual processor instances comprises concurrently executing the load instruction by each virtual processor instance of the plurality of virtual processor instances.

3. The one or more computer storage media of claim 1 , wherein instantiating, within the application software development environment, a plurality of virtual processor instances comprises:
instantiating at least one virtual processor instance for each location in the output image array; and
assigning respective threads executed by the plurality of virtual processor instances to respective line group positions corresponding respectively to locations of image data in the output image array.

4. The one or more computer storage media of claim 1 , wherein executing a same load instruction by the plurality of virtual processor instances causes each virtual processor instance to read from a different respective location in the input image array.

5. The one or more computer storage media of claim 1 , wherein the operations further comprise:
receiving a store instruction of the instruction set architecture of the virtual processor instances, wherein the store instruction identifies a source register and specifies a store address, the store address having a target x offset and a target y offset, the target x offset and the target y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned; and
executing the store instruction by each virtual processor instance, including:
obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
computing a two-dimensional target position in the line group of the image including using the target x offset and the target y offset of the store address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
copying, to a location in the output image array corresponding to the computed two-dimensional target position in the line group of the image, data from a source register of the virtual processor instance identified by the store instruction.

6. The one or more computer storage media of claim 5 , wherein executing a same store instruction by the plurality of virtual processor instances causes each virtual processor instance to write to a different respective location in the output image array.

7. The one or more computer storage media of claim 5 , wherein after executing the store instruction by each virtual processor instance of the plurality of virtual processor instances, the input image array remains unchanged.

8. A system comprising:
one or more computers and one or more storage devices storing instructions that are operable, when executed by the one or more computers, to cause the one or more computers to perform operations comprising:
instantiating, within an application software development environment, an input array, an output array, and a plurality of virtual processor instances, wherein the input array stores input image data of one or more line groups of an image, and wherein the output array stores output image data of one or more line groups of the image, wherein each virtual processor instance comprises one or more registers, each virtual processor instance being configured to execute instructions of an instruction set architecture having a load instruction that references locations within the input array of the application software development environment, and wherein each virtual processor instance is configured to execute a respective thread of a plurality of threads, wherein each thread is assigned to a respective line group position within a line group of the image;
receiving a load instruction of the instruction set architecture of the virtual processor instances, wherein the load instruction identifies a target register and specifies a load address having a source x offset and a source y offset, the source x offset and the source y offset being offsets relative to a line group position to which a thread executed by a virtual processor instance is assigned;
executing a respective thread having the load instruction by each virtual processor instance of the plurality of virtual processor instances thereby simulating operations of an image processor having a two-dimensional shift register array and a two-dimensional array of processing elements, wherein executing the load instruction includes:
obtaining a line group position to which a thread executed by the virtual processor instance is assigned,
computing a two-dimensional source position in the line group of the image including using the source x offset and the source y offset of the load address as offsets relative to the line group position to which the thread executed by the virtual processor instance is assigned, and
copying, to a target register of the virtual processor instance identified by the load instruction, data from a location in the input image array corresponding to the computed two-dimensional source position in the line group of the image.

9. The system of claim 8 , wherein executing the load instruc

Assignees

• Google Llc

Inventors

• Meixner Albert
• Shacham Ofer
• Patterson David
• Finchelstein Daniel Frederic
• Zhu Qiuling
• Redgrave Jason Rupert

Classifications

• G06F9/44

  Arrangements for executing specific programs · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F8/10

  Requirements analysis; Specification techniques · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title