Methods and apparatus providing thermal isolation of photonic devices

Patent metadata

Field	Value
Publication number	US-10090451-B2
Application number	US-201615056845-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Jun 15, 2012
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices. Methods of fabricating such circuits and systems are also described.

First claim

We claim:

1. A method of forming an integrated circuit, the method comprising:
providing a substrate;
forming a trench in an upper surface of the substrate;
forming a temperature-sensitive photonic device above the substrate and separated from the trench by a portion of the substrate;
forming a heating device above the substrate and over the trench such that the trench extends under the entirety of the heating device, wherein the heating device is configured to dissipate heat toward the photonic device; and
forming a thermal isolation region in the trench, wherein the thermal isolation region reduces dissipation of heat from the heating device into the substrate in the direction of the isolation region,
wherein the trench does not extend underneath any portion of the temperature-sensitive photonic device.

2. The method of claim 1 , wherein forming the thermal isolation region comprises forming a region of low thermal conductivity material that is less thermally conductive than material in the area of the die in which the thermal isolation region is formed.

3. The method of claim 2 , wherein forming the region of low thermal conductivity material comprises: etching the trench in the substrate; and depositing the low thermal conductivity material in the trench.

4. The method of claim 3 , wherein depositing the low thermal conductivity material in the trench comprises doping silicon dioxide with a material having a lower dielectric constant than the silicon dioxide.

5. The method of claim 3 , wherein depositing the low thermal conductivity material in the trench comprises depositing porous silicon dioxide.

6. The method of claim 3 , wherein depositing the low thermal conductivity material in the trench comprises depositing silicon dioxide using spin-on deposition.

7. The method of claim 2 , wherein forming a region of low thermal conductivity material comprises forming an insulating layer between the substrate and the heating device.

8. The method of claim 7 , wherein the insulating layer comprises an oxide doped with a material having a lower thermal conductivity than the oxide.

9. The method of claim 7 , wherein the insulating layer comprises porous silicon dioxide.

10. The method of claim 7 , wherein the insulating layer comprises spin-on silicon dioxide.

11. The method of claim 1 , wherein forming the thermal isolation region comprises forming a physical gap between the heating device and material adjacent to a portion of the heating device.

12. The method of claim 11 , wherein the gap is formed in the substrate.

13. The method of claim 11 , wherein the gap is formed in a region above the substrate.

14. The method of claim 11 , wherein forming the gap comprises performing a silicon etch to remove a portion of material adjacent to the heating device.

15. The method of claim 11 , wherein forming the gap comprises performing a vacuum process to remove a portion of material adjacent to the heating device.

16. The method of claim 1 , wherein the thermal isolation region is formed prior to forming the heating device.

17. The method of claim 1 , wherein the thermal isolation region is formed after forming the heating device.

18. The method of claim 17 , further comprising: forming an opening near the heating device, wherein the opening passes into the substrate; and forming the thermal isolation region under the heating device.

Assignees

• Micron Technology Inc

Inventors

• Meade Roy
• Sandhu Gurtej

Classifications

• H01L2933/0075

  Electricity · mapped topic

• H01L33/64 Primary

  Electricity · mapped topic

• G02F1/3133

  the optical waveguides being made of semiconducting materials · CPC title

• G02B2006/121

  Channel; buried or the like · CPC title

• G02B6/12007 Primary

  forming wavelength selective elements, e.g. multiplexer, demultiplexer · CPC title