Methods and apparatus providing thermal isolation of photonic devices

Patent metadata

Field	Value
Publication number	US-9310552-B2
Application number	US-201213524446-A
Country	US
Kind code	B2
Filing date	Jun 15, 2012
Priority date	Jun 15, 2012
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices. Methods of fabricating such circuits and systems are also described.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. An integrated structure comprising:
a substrate having an upper surface;
a first trench formed in the upper surface of the substrate;
a device formation region over the upper surface of the substrate;
a first temperature-sensitive photonic device formed in the device formation region;
a waveguide formed in the device formation region and separated from the trench by a portion of the substrate;
a heating device formed in the device formation region for heating the first temperature-sensitive photonic device, wherein the heating device is located over the first trench; and
a first thermal isolation region formed under the heating device, wherein the first thermal isolation region is located in the first trench, such that the first thermal isolation region is provided in the upper surface of the substrate, and wherein the first thermal isolation region reduces dissipation of heat from the heating device into the substrate.

2. The integrated structure of claim 1 , wherein the first trench and first thermal isolation region are formed under the heating device and at least a portion of the first temperature-sensitive photonic device, and wherein the first thermal isolation region is not formed under the wavelength.

3. The integrated structure of claim 1 , wherein the first thermal isolation region comprises a low thermal conductivity material within the first trench.

4. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises an oxide doped with a material having a lower thermal conductivity than the oxide.

5. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises porous silicon dioxide.

6. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises spin-on silicon dioxide.

7. The integrated structure of claim 1 , wherein the heating device is mechanically supported by at least one interconnect extending into the device formation region.

8. The integrated structure of claim 2 , wherein the first trench and first thermal isolation region are formed under the entirety of the first temperature sensitive photonic device.

9. The integrated structure of claim 8 , further comprising a second photonic device formed in the device formation region and wherein the first trench and first thermal isolation region are formed under the second photonic device.

10. The integrated structure of claim 1 , further comprising a second photonic device formed in the device formation region and further comprising a second trench provided in an upper surface of the substrate and a second thermal isolation region under the second photonic device.

11. The integrated structure of claim 2 , wherein the substrate comprises a bulk silicon substrate and the first trench and first thermal isolation region are provided in an upper surface of the silicon.

12. The integrated structure of claim 2 , wherein the substrate comprises a silicon on insulator substrate and the first trench and first thermal isolation region are provided in the insulator of the silicon on insulator substrate.

13. The integrated structure of claim 2 , wherein the first trench and first thermal isolation region form a shallow trench isolation region.

14. The integrated structure of claim 10 , wherein the second thermal isolation region comprises a gap provided in the second trench between the second photonic device and substrate.

15. The integrated structure of claim 3 , wherein the low thermal conductivity material has a thermal conductivity that is less than approximately 0.006 W/cm° C.

16. The integrated structure of claim 3 , wherein the low thermal conductivity material comprises silicon dioxide that has been doped with a dopant having a lower dielectric constant than the silicon dioxide.

17. The integrated structure of claim 16 , wherein the dopant comprises fluorine.

18. The integrated structure of claim 16 , wherein the dopant comprises carbon.

19. The integrated structure of claim 1 , further comprising a second thermal isolation region formed within the first thermal isolation region.

20. The integrated structure of claim 1 , wherein the first temperature-sensitive photonic device comprises a carrier wave modulator.

21. The integrated structure of claim 1 , wherein the first temperature-sensitive photonic device comprises a laser.

22. The integrated structure of claim 19 , wherein the second thermal isolation region has a different thermal conductivity than the first thermal isolation region.

23. The integrated structure of claim 22 , wherein the second thermal isolation region has a lower thermal conductivity than the first thermal isolation region.

24. The integrated structure of claim 19 , wherein the second thermal isolation region comprises a physical gap within the first thermal isolation region.

Assignees

• Meade Roy
• Sandhu Gurtej
• Micron Technology Inc

Inventors

• Meade Roy
• Sandhu Gurtej

Classifications

• H10H20/0365

  of means for heat extraction or cooling · CPC title

• H10H20/858 Primary

  Means for heat extraction or cooling · CPC title

• G02F1/3133

  the optical waveguides being made of semiconducting materials · CPC title

• G02F1/3132

  of directional coupler type · CPC title

• G02B6/12 Primary

  of the integrated circuit kind (electric integrated circuits H10B, H10D84/00 - H10D89/00, H10F19/00, H10F39/00, H10H29/00, H10K19/00, H10K39/00, H10K59/00, H10N19/00, H10N39/00, H10N59/00, H10N69/00, H10N79/00, H10N89/00) · CPC title