Isolation well doping with solid-state diffusion sources for FinFET architectures

Patent metadata

Field	Value
Publication number	US-10090304-B2
Application number	US-201314914614-A
Country	US
Kind code	B2
Filing date	Sep 25, 2013
Priority date	Sep 25, 2013
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.

First claim

What is claimed is:

1. An integrated microelectronic device comprising:
a substrate;
a transistor including a non-planar semiconductor fin extending from the substrate, the fin having a sub-fin region between an active region of the fin and the substrate, wherein the sub-fin region further comprises a lower sub-fin region proximate to the substrate and an upper sub-fin region proximate to the active region;
an impurity source film adjacent to a sidewall surface of the lower sub-fin region and absent from a sidewall surface of the upper sub-fin region, wherein the impurity source film comprises an impurity present in the lower sub-fin region; and
a gate stack adjacent to a sidewall surface of the active region, wherein the gate stack comprises a gate dielectric and a gate electrode.

2. The device of claim 1 , further comprising an isolation dielectric over the impurity source film and adjacent to a sidewall surface of the upper sub-fin region, wherein the isolation dielectric is substantially free of the impurity present in the impurity source film.

3. The device of claim 1 , further comprising:
a second impurity source film comprising a second impurity, the second impurity source film over the impurity source film and adjacent to the sidewall surface of the upper sub-fin region, wherein the upper sub-fin region comprises the second impurity and has a conductivity type complementary to that of the lower sub-fin region.

4. The device of claim 1 , further comprising:
a second impurity source film comprising a second impurity, the second impurity source film over the impurity source film and adjacent to a sidewall surface of the upper sub-fin region, wherein the upper sub-fin region comprises the second impurity and has a conductivity type complementary to that of the lower sub-fin region; and
a second transistor including a second non-planar semiconductor fin extending from the substrate, the second fin having a second sub-fin region between a second active region of the second fin and the substrate, wherein the second sub-fin region further comprises a second lower sub-fin region proximate to the substrate and a second upper sub-fin region proximate to the second active region, wherein the impurity source film is adjacent to a sidewall surface of the second lower sub-fin region and is absent from the second upper sub-fin region, and an isolation dielectric is over the impurity source film and adjacent to a sidewall surface of the second upper sub-fin region, wherein the isolation dielectric, as deposited, is substantially free of the impurities present in the impurity source film or the second impurity source film.

5. The device of claim 1 , wherein the lower sub-fin region comprises an impurity distinct from that of the upper sub-fin region.

6. The device of claim 1 , wherein the impurity in the lower sub-fin region induces a conductivity type in the lower sub-fin region that is complementary to that of the substrate.

7. The device of claim 1 , wherein the upper sub-fin region comprises an impurity distinct from both the lower sub-fin region and the active region.

8. The device of claim 1 , wherein the upper sub-fin region comprises an impurity complementary to the lower sub-fin region.

9. The device of claim 1 , wherein:
the fin has a lateral width less than 20 nm, and extends up from the substrate by 20-150 nm;
the impurity source film comprises a silicate glass film having a thickness between 1 nm and 7 nm; and
the impurity within the lower sub-fin region has a concentration between 10 17 cm −3 and 10 19 cm 3 .

10. The device of claim 4 , further comprising:
a third transistor including a third non-planar semiconductor fin extending from the substrate, the third fin having a third sub-fin region between a third active region of the third fin and the substrate, wherein the third sub-fin region further comprises a third lower sub-fin region proximate to the substrate and a third upper sub-fin region proximate to the third active region, and wherein
the impurity source film is absent from sidewall surfaces of the third lower sub-fin region and third upper sub-fin region.

11. The device of claim 1 , further comprising:
a second impurity source film comprising a second impurity, the second impurity source film over the impurity source film and adjacent to a sidewall surface of the upper sub-fin region, wherein the upper sub-fin region comprises the second impurity;
a second transistor including a second non-planar semiconductor fin extending from the substrate, the second fin having a second sub-fin region between a second active region of the second fin and the substrate, wherein:
the second sub-fin region further comprises a second lower sub-fin region proximate to the substrate and a second upper sub-fin region proximate to the second active region;
the impurity source film is adjacent to a sidewall surface of the second lower sub-fin region and absent from the second upper sub-fin region;
an isolation dielectric material is over the impurity source film and adjacent to a sidewall surface of the second upper sub-fin region, wherein the isolation-dielectric is substantially free of the impurities present in the impurity source film or the second impurity source film; and
a second gate stack adjacent to a sidewall surface of the second active region, wherein the second gate stack comprises a gate dielectric and a gate electrode that are above the isolation dielectric;

a third transistor including a third non-planar semiconductor fin extending from the substrate, the third fin having a third sub-fin region between a third active region of the third fin and the substrate, wherein:
the impurity source film is absent from sidewall surfaces of the third sub-fin region;
the second impurity source film is adjacent to a sidewall surface of the third sub-fin region; and
a third gate stack is adjacent to a sidewall surface of the third active region, wherein:

the impurity source film and the second impurity source film each comprise a silicate glass;
the lower sub-fin region and the second lower sub-fin region is n-type;
a surface layer in a first region of the substrate separating the lower sub-fin region from the second lower sub-fin region is n-type; and
a sub-surface region of the substrate below the surface layer in the first region, and a surface layer in a second region of the substrate separating the third sub-fin region from the sub-fin region and the second lower sub-fin region, is p-type.

12. The device of claim 1 , wherein:
the impurity source film comprises a phosphorus-doped silicate glass (PSG); and
the impurity is phosphorus.

13. The device of claim 1 , wherein:
the active region has a lateral width less than 20 nm;
the fin has a vertical height of between 20 nm and 150 nm; and
the impurity source film has a thickness between 1 nm and 5 nm as measured normal to the sidewall surface.

14. The device of claim 3 , wherein:
at least one of the impurity source film and the second impurity source film comprises a phosphorus-doped silicate glass (PSG); and
the impurity is phosphorus.

15. The device of claim 4 , wherein the isolation dielectric comprises a plurality of dielectric material layers including a silicon nitride layer that is adjacent to the impurity source film, and adjacent to the second impurity source film.

16. The device of claim 4 , wherein:
the impurity source film comprises a phosphorus-doped silicate glass (PSG);
the fin is associated with a PMOS transistor;
the second impurity source film comprises a boron-doped silicate glas

Assignees

• Hafez Walid M
• Jan Chia Hong
• Yeh Jeng Ya D
• Chang Hsu Yu
• Dias Neville
• Munasinghe Chanaka
• Intel Corp

Inventors

• Jan Chia-Hong
• Hafez Walid M
• Yeh Jeng-Ya David
• Chang Hsu-Yu
• Dias Neville L
• Munasinghe Chanaka D

Classifications

• H10P32/1412

  through the applied layer · CPC title

• H10P32/171

  being group IV material · CPC title

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic