Semiconductor device and method of manufacture

Patent metadata

Field	Value
Publication number	US-10090284-B2
Application number	US-201715859123-A
Country	US
Kind code	B2
Filing date	Dec 29, 2017
Priority date	May 17, 2016
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

First claim

What is claimed is:

1. A method comprising:
forming a first Integrated Passive Device Structure (IPDS), comprising:
forming an integrated passive device on a first substrate; and
forming a first through substrate via (TSV) in the first substrate;

forming a first via on a second substrate;
disposing a first semiconductor device and the first IPDS on the second substrate, wherein the first semiconductor device, the first IPDS, and the first via are separated from each other;
encapsulating the first semiconductor device, the first IPDS, and the first via with a first encapsulant, wherein the first via extends from a first side of the encapsulant to a second side of the encapsulant; and
forming a first redistribution layer (RDL) over the first side of the encapsulant, wherein the first RDL is electrically connected to the first semiconductor device, the first IPDS, and the first via.

2. The method of claim 1 , wherein forming the integrated passive device comprises forming a deep-trench capacitor.

3. The method of claim 1 , wherein forming a first IPDS further comprises forming a metallization layer over the substrate, and wherein the first RDL is electrically connected to the integrated passive device through the metallization layer.

4. The method of claim 1 , further comprising:
forming a second IPDS; and
disposing the second IPDS on the second substrate.

5. The method of claim 1 , wherein the first IPDS is disposed on the second substrate using a pick-and-place process.

6. The method of claim 1 , further comprising attaching a second semiconductor device to the second side of the encapsulant, wherein the second semiconductor device is electrically connected to the first RDL through the first via and through the first TSV.

7. The method of claim 1 , further comprising planarizing the first semiconductor device, the first IPDS, the first via, and the first encapsulant.

8. A method comprising:
attaching a die to a first side of a first substrate;
attaching a plurality of interconnect structures to the first side of the first substrate, each interconnect structure comprising:
a second substrate;
at least one integrated passive device; and
at least one conductive element extending from a first side of the second substrate to a second side of the second substrate;

forming a plurality of through substrate vias (TSVs) on the first side of the first substrate;
forming a molding compound surrounding the die, the plurality of interconnect structures, and the plurality of TSVs, wherein the die, each interconnect structure of the plurality of interconnect structures, and each TSV of the plurality of TSVs are separated by the molding compound; and
forming a first redistribution layer (RDL) over the die, the plurality of interconnect structures, and the plurality of TSVs.

9. The method of claim 8 , wherein the first substrate comprises a polymer layer.

10. The method of claim 8 , wherein the plurality of TSVs surround the die.

11. The method of claim 8 , further comprising attaching a package to the second side of the first substrate, wherein the package comprises a plurality of contact pads that are electrically connected to the plurality of TSVs and to the plurality of interconnect structures.

12. The method of claim 11 , wherein the package is electrically connected to the die through the first RDL.

13. The method of claim 8 , further comprising forming a plurality of external connections on the first RDL.

14. The method of claim 8 , wherein at least one interconnect structure of the plurality of interconnect structures comprises a second RDL disposed over the second substrate, wherein the second RDL is electrically connected to the at least one conductive element.

15. The method of claim 8 , further comprising performing a planarization process on the molding compound, the plurality of interconnect structures, the plurality of TSVs, and the die.

16. A method of manufacturing a semiconductor device, the method comprising:
forming a set of vias on a redistribution layer (RDL);
placing a die on the RDL separated from the set of vias; and
placing a first interconnect structure on the RDL, the first interconnect structure separated from the die and the set of vias, the first interconnect structure comprising:
a substrate;
at least one through conductive element extending from one side of the substrate to a second side of the substrate; and
at least one integrated passive device;

encapsulating the set of vias, the die, and the first interconnect structure in an encapsulant, wherein the encapsulant is in physical contact with the set of vias, the die, and the first interconnect structure; and
planarizing the set of vias, the die, the encapsulant, and the first interconnect structure.

17. The method of claim 16 , wherein placing a first interconnect structure on the RDL comprises a pick-and-place process.

18. The method of claim 16 , further comprising placing a top package over the set of vias, the die, and the first interconnect structure, wherein the top package is connected to the set of vias and the first interconnect structure.

19. The method of claim 16 , further comprising placing a second interconnect structure on the RDL.

20. The method of claim 16 , wherein the at least one integrated passive device is a trench capacitor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Yang Tien-Chung
• Su An-Jhih
• Chen Hsien-Wei

Classifications

• H10W70/6525

  for securing the interconnections to the substrate, e.g. to prevent peeling · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title